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ST16C2550
9
Rev. 3.40
FIFO Operation
The 16 byte transmit and receive data FIFO’s are
enabled by the FIFO Control Register (FCR) bit-0. The
user can set the receive trigger level via FCR bits 6-7 but
not the transmit trigger level. The receiver FIFO section
includes a time-out function to ensure data is delivered
to the external CPU. An interrupt is generated whenever
the Receive Holding Register (RHR) has not been read
following the loading of a character or the receive trigger
level has not been reached.
Hardware/Software and Time-out Interrupts
The interrupts are enabled by IER bits 0-3. Care must
be taken when handling these interrupts. Following a
reset, if Interrupt Enable Register (IER) bit-1 = 1, the
2550 will issue a Transmit Holding Register interrupt.
This interrupt must be serviced prior to continuing
operations. The LSR register provides the current singu-
lar highest priority interrupt only. It could be noted that
CTS and RTS interrupts have lowest interrupt priority. A
condition can exist where a higher priority interrupt may
mask the lower priority CTS/RTS interrupt(s). Only after
servicing the higher pending interrupt will the lower
priority CTS/ RTS interrupt(s) be
reflected in the status register. Servicing the interrupt
without investigating further interrupt conditions can
result in data errors.
When two interrupt conditions have the same priority, it
is important to service these interrupts correctly. Re-
ceive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER bit-3). The
receiver issues an interrupt after the number of charac-
ters have reached the programmed trigger level. In this
case the 2550 FIFO may hold more characters than the
programmed trigger level. Following the removal of a
data byte, the user should recheck LSR bit-0 for
additional characters. A Receive Time Out will not occur
if the receive FIFO is empty. The time out counter is
reset at the center of each stop bit received or each time
the receive holding register (RHR) is read.. The actual
time out value is T (
T
ime out length in bits) = 4 X P
(
P
rogrammed word length) + 12. To convert the time out
value to a character value, the user has to consider the
complete word length, including data information
length, start bit, parity bit, and the size of stop bit, i.e.,
1X, 1.5X, or 2X bit times.
Example -A: If the user programs a word length of 7,
with no parity and one stop bit, the time out will be:
T = 4 X 7( programmed word length) +12 = 40 bit times.
The character time will be equal to 40 / 9 = 4.4
characters, or as shown in the fully worked out example:
T = [(programmed word length = 7) + (stop bit = 1) +
(start bit = 1) = 9]. 40 (bit times divided by 9) = 4.4
characters.
Example -B: If the user programs the word length = 7,
Table 3, INTERNAL REGISTERS DECODING
A2
A1
A0
READ MODE
WRITE MODE
CONDITION(S)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
Receive Holding Register
Interrupt Enable Register
Interrupt Status Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
N.A.
N.A.
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
LCR bit-7 = 0
LCR bit-7 = 0
None
None
None
None
None
None
LCR bit-7 = 1
LCR bit-7 = 1