参数资料
型号: ST16C2550CJ44
厂商: STARTECH SEMICONDUCTOR INC
元件分类: 微控制器/微处理器
英文描述: DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFO’S
中文描述: 2 CHANNEL(S), 448K bps, SERIAL COMM CONTROLLER, PQCC44
文件页数: 21/34页
文件大小: 443K
代理商: ST16C2550CJ44
ST16C2550
21
Rev. 3.20
Interrupt will be generated.
MSR BIT-1:
Logic 0 = No -DSR Change. (normal default condition)
Logic 1 = The -DSR input to the 2550 has changed
state since the last time it was read. A modem Status
Interrupt will be generated.
MSR BIT-2:
Logic 0 = No -RI Change. (normal default condition)
Logic 1 = The -RI input to the 2550 has changed from
a logic 0 to a logic 1. A modem Status Interrupt will be
generated.
MSR BIT-3:
Logic 0 = No -CD Change. (normal default condition)
Logic 1 = Indicates that the -CD input to the has
changed state since the last time it was read. A
modem Status Interrupt will be generated.
MSR BIT-4:
During normal operation, this bit is the compliment of
the -CTS input. During the loop-back mode this bit is
equivalent to MCR bit-1 (-RTS).
MSR BIT-5:
During normal operation, this bit is the compliment of
the -DSR input. During the loop-back mode, this bit is
equivalent to MCR bit-0 (-DTR).
MSR BIT-6:
During normal operation, this bit is the compliment of
the -RI input. Reading this bit in the loop-back mode
produces the state of MCR bit-2 (-OP1)
MSR BIT-7:
During normal operation, this bit is the compliment of
the -CD input. Reading this bit in the loop-back mode
produces the state of MCR bit-3 (-OP2).
Note: Whenever any MSR bit 0-3: is set to logic 1, a
MODEM Status Interrupt will be generated.
Scratchpad Register (SPR)
The ST16C2550 provides a temporary data register to
store 8 bits of user information.
ST16C2550 EXTERNAL RESET CONDITION
REGISTERS
RESET STATE
IER
ISR
LCR
MCR
LSR
IER BITS 0-7=0
ISR BIT-0=1, ISR BITS 1-7=0
LCR BITS 0-7=0
MCR BITS 0-7=0
LSR BITS 0-4=0,
LSR BITS 5-6=1 LSR, BIT 7=0
MSR BITS 0-3=0,
MSR BITS 4-7=input signals
FCR BITS 0-7=0
MSR
FCR
SIGNALS
RESET STATE
TX
-OP2
-RTS
-DTR
INT
High
High
High
High
Three state mode
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