- 您现在的位置：买卖IC网 > PDF目录384931 > ST16C2550IQ48 (EXAR CORP) DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFO’S PDF资料下载
参数资料
| 型号： | ST16C2550IQ48 |
| 厂商： | EXAR CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFO’S |
| 中文描述： | 2 CHANNEL(S), 4M bps, SERIAL COMM CONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, 1 MM HEIGHT, TQFP-48 |
| 文件页数： | 16/34页 |
| 文件大小： | 443K |
| 代理商： | ST16C2550IQ48 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页当前第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页
ST16C2550
16
Rev. 3.20
E) LSR BIT-7 will show if any FIFO data errors
occurred.
IER BIT-0:
In the 16C450 mode, This interrupt will be issued when
the RHR has data or is cleared when the RHR is
empty. In the FIFO mode, this interrupt will be issued
when the FIFO has reached the programmed trigger
level or is cleared when the FIFO drops below the
trigger level.
Logic 0 = Disable the receiver ready (ISR level 2,
RXRDY) interrupt. (normal default condition)
Logic 1 = Enable the RXRDY (ISR level 2) interrupt.
IER BIT-1:
In the 16C450 mode, this interrupt will be issued
whenever the THR is empty and is associated with bit-
5 in the LSR register. In the FIFO modes, this interrupt
will be issued whenever the FIFO and THR are empty
Logic 0 = Disable the Transmit Holding Register
Empty (TXRDY) interrupt. (normal default condition)
Logic 1 = Enable the TXRDY (ISR level 3) interrupt.
IER BIT-2:
This interrupt will be issued whenever an receive data
error condition exists as reflected in LSR bits 1-4.
Logic 0 = Disable the receiver line status interrupt.
(normal default condition)
Logic 1 = Enable the receiver line status interrupt.
IER BIT-3:
This interrupt will be issued whenever there is a
modem status change as reflected in MSR bits 0-3.
Logic 0 = Disable the modem status register interrupt.
(normal default condition)
Logic 1 = Enable the modem status register interrupt.
IER BIT 4-7:
Not Used - initialized to a logic 0.
FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the
FIFOs, set the receive FIFO trigger levels, and select
the DMA mode. The DMA, and FIFO modes are
defined as follows:
DMA MODE
Mode 0
single transmit or receive operation, and is similar to
the ST16C450 mode. Transmit Ready (-TXRDY) on
44/48 pin packages will go to a logic 0 when ever an
empty transmit space is available in the Transmit
Holding Register (THR). Receive Ready (-RXRDY) on
44,/48 pin packages will go to a logic 0 whenever the
Receive Holding Register (RHR) is loaded with a
character.
Mode 1
Set and enable the interrupt in a block
mode operation. The transmit interrupt is set when the
transmit FIFO is below the programmed trigger level.
-TXRDY on 44/48 pin packages remains a logic 0 as
long as one empty FIFO location is available. The
receive interrupt is set when the receive FIFO fills to
the programmed trigger level. However the FIFO
continues to fill regardless of the programmed level
until the FIFO is full. -RXRDY on 44/48 pin packages
remains a logic 0 as long as the FIFO fill level is above
the programmed trigger level.
Set and enable the interrupt for each
FCR BIT-0:
Logic 0 = Disable the transmit and receive FIFO.
(normal default condition)
Logic 1 = Enable the transmit and receive FIFO. This
bit must be a 1 when other FCR bits are written to or
they will not be programmed.
FCR BIT-1:
Logic 0 = No FIFO receive reset. (normal default
condition)
Logic 1 = Clears the contents of the receive FIFO and
resets the FIFO counter logic (the receive shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
FCR BIT-2:
Logic 0 = No FIFO transmit reset. (normal default
condition)
Logic 1 = Clears the contents of the transmit FIFO and
resets the FIFO counter logic (the transmit shift regis-
ter is not cleared or altered). This bit will return to a
logic 0 after clearing the FIFO.
相关PDF资料 |
PDF描述 |
|---|---|
| ST16C2550 | Dual UART with 16-Byte of Transmit and Receive FIFO(双通用异步接收器/发送器（带16字节接收和发送先进先出）) |
| ST16C2552 | Dual UART with 16-Byte Transmit and Receive FIFO(双通用异步接收器/发送器（带16字节接收和发送先进先出）) |
| ST16C450 | UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) |
| ST16C450CJ44 | UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) |
| ST16C450CP40 | UNIVERSAL ASYNCHRONOUS RECEIVER/TRANSMITTER (UART) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST16C2550IQ48-F | 功能描述:UART 接口集成电路 2.97V-5.5V 16B FIFO temp -45 to 85C;UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C2550IQ48TR-F | 功能描述:UART 接口集成电路 DUAL UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C2552 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO |
| ST16C2552_06 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO |
| ST16C2552CJ | 制造商:EXAR 功能描述:IC , Dual UART 4MBPS 5.5 44 PLCC 制造商:Exar Corporation 功能描述: 制造商:XIC 功能描述: 制造商:Exar Corporation 功能描述:UART, 44 Pin, Plastic, PLCC |
发布紧急采购，3分钟左右您将得到回复。