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参数资料
| 型号： | ST16C2550IQ48 |
| 厂商： | EXAR CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | DUAL UART WITH 16-BYTE TRANSMIT AND RECEIVE FIFO’S |
| 中文描述： | 2 CHANNEL(S), 4M bps, SERIAL COMM CONTROLLER, PQFP48 |
| 封装： | 7 X 7 MM, 1 MM HEIGHT, TQFP-48 |
| 文件页数： | 9/34页 |
| 文件大小： | 443K |
| 代理商： | ST16C2550IQ48 |
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ST16C2550
9
Rev. 3.20
Table 3, INTERNAL REGISTER DECODE
A2
A1
A0
READ MODE
WRITE MODE
General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR): Note 1*
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Receive Holding Register
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
Interrupt Status Register
Line Status Register
Modem Status Register
Scratchpad Register
Scratchpad Register
Baud Rate Register Set (DLL/DLM): Note *2
0
0
0
0
0
1
LSB of Divisor Latch
MSB of Divisor Latch
LSB of Divisor Latch
MSB of Divisor Latch
Note 1* The General Register set is accessible only when CS A/B is a logic 0.
Note 2* The Baud Rate register set is accessible only when CS A/B is a logic 0 and LCR bit-7 is a logic 1.
FIFO Operation
The 16 byte transmit and receive data FIFOs are
enabled by the FIFO Control Register (FCR) bit-0. The
user can set the receive trigger level via FCR bits 6-
7 but not the transmit trigger level. The transmit
interrupt trigger level is set to 16 following a reset. The
receiver FIFO section includes a time-out function to
ensure data is delivered to the external CPU. An
interrupt is generated whenever the Receive Holding
Register (RHR) has not been read following the load-
ing of a character or the receive trigger level has not
been reached.
Hardware/Software and Time-out Interrupts
The interrupts are enabled by IER bits 0-3. Care must
be taken when handling these interrupts. Following a
reset the transmitter interrupt is enabled, the 2550 will
issue an interrupt to indicate that transmit holding
register is empty. This interrupt must be serviced prior
to continuing operations. The LSR register provides
the current singular highest priority interrupt only. It
could be noted that CTS and RTS interrupts have
lowest interrupt priority. A condition can exist where a
higher priority interrupt may mask the lower priority
CTS/RTS interrupt(s). Only after servicing the higher
pending interrupt will the lower priority CTS/ RTS
interrupt(s) be reflected in the status register. Servic-
ing the interrupt without investigating further interrupt
conditions can result in data errors.
When two interrupt conditions have the same priority,
it is important to service these interrupts correctly.
Receive Data Ready and Receive Time Out have the
same interrupt priority (when enabled by IER bit-3).
The receiver issues an interrupt after the number of
characters have reached the programmed trigger
level. In this case the 2550 FIFO may hold more
characters than the programmed trigger level. Follow-
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST16C2550IQ48-F | 功能描述:UART 接口集成电路 2.97V-5.5V 16B FIFO temp -45 to 85C;UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C2550IQ48TR-F | 功能描述:UART 接口集成电路 DUAL UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C2552 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO |
| ST16C2552_06 | 制造商:EXAR 制造商全称:EXAR 功能描述:2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO |
| ST16C2552CJ | 制造商:EXAR 功能描述:IC , Dual UART 4MBPS 5.5 44 PLCC 制造商:Exar Corporation 功能描述: 制造商:XIC 功能描述: 制造商:Exar Corporation 功能描述:UART, 44 Pin, Plastic, PLCC |
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