- 您现在的位置：买卖IC网 > PDF目录299932 > ST16C2552CJ44 (EXAR CORP) 2 CHANNEL(S), 4M bps, SERIAL COMM CONTROLLER, PQCC44 PDF资料下载
参数资料
| 型号： | ST16C2552CJ44 |
| 厂商： | EXAR CORP |
| 元件分类： | Serial IO/Communication Controller |
| 英文描述： | 2 CHANNEL(S), 4M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 14/38页 |
| 文件大小： | 447K |
| 代理商： | ST16C2552CJ44 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页当前第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页
ST16C2552
19
REV. 4.2.1
2.97V TO 5.5V DUAL UART WITH 16-BYTE FIFO
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 8).
ISR[5:4]: Reserved
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
4.6
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and
select the DMA mode. The DMA, and FIFO modes are defined as follows:
FCR[0]: TX and RX FIFO Enable
Logic 0 = Disable the transmit and receive FIFO (default).
Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No receive FIFO reset (default)
Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
Logic 0 = No transmit FIFO reset (default).
Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[3]: DMA Mode Select
Controls the behavior of the TXRDY# and RXRDY# pins. See DMA operation section for details.
Logic 0 = Normal Operation (default).
Logic 1 = DMA Mode.
FCR[5:4]: Reserved
FCR[7:6]: Receive FIFO Trigger Select
(logic 0 = default, RX trigger level =1)
These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when
the number of the characters in the FIFO crosses the trigger level. Table 9 shows the complete selections.
TABLE 9: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION
FCR
BIT-7
FCR
BIT-6
RECEIVE
TRIGGER
LEVEL
COMPATIBILITY
0
1
0
1
0
1
1 (default)
4
8
14
Table-A. 16C550,
16C2550, 16C2552,
16C554, 16C580 com-
patible.
相关PDF资料 |
PDF描述 |
|---|---|
| ST16C552CJ68 | 2 CHANNEL(S), SERIAL COMM CONTROLLER, PQCC68 |
| ST16C554DCJ68 | 4 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC68 |
| ST1803DHI | High Voltage Fast-Switching NPN Power Transistor(高电压快速开关NPN功率晶体管) |
| ST180S16P1PBF | 314 A, 1600 V, SCR, TO-209AB |
| ST1W008S4A | 8 CONTACT(S), MALE, PCMCIA CONNECTOR, SOLDER |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ST16C2552CJ44-F | 功能描述:UART 接口集成电路 2.97V-5.5V 16B FIFO temp 0C to 70C; UART RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C2552CJ44TR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Exar Corporation 功能描述: |
| ST16C2552CJ44TR-F | 功能描述:UART 接口集成电路 DUAL UART W/16BYTE FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| ST16C2552CQ48 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:UART |
| ST16C2552IJ | 制造商:Exar Corporation 功能描述:2 CHANNEL(S), 4M bps, SERIAL COMM CONTROLLER, PQCC44 |
发布紧急采购，3分钟左右您将得到回复。