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参数资料
型号： ST52F510Y3B6
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDIP16
封装： PLASTIC, DIP-16
文件页数： 91/106页
文件大小： 648K
代理商： ST52F510Y3B6
ST52F510/F513/F514
85/106
14 I2C BUS INTERFACE (I2C)
14.1 Introduction
The I2C Bus Interface serves as an interface
between the microcontroller and the serial I2Cbus,
providing both multimaster and slave functions and
controls all I
2C bus-specific sequencing, protocol,
arbitration and timing. The
I2Bus Interface
supports fast I2C mode (400kHz).
14.2 Main Features
s
Parallel-bus/I2C protocol converter
s
Multi-master capability
s
7-bit/10-bit Addressing
s
Transmitter/Receiver flag
s
End-of-byte transmission flag
s
Transfer problem detection
I
2C Master Features:
s
Clock generation
s
I
2C bus busy flag
s
Arbitration Lost Flag
s
End of byte transmission flag
s
Transmitter/Receiver Flag
s
Start bit detection flag
s
Start and Stop generation
I2C Slave Features:
s
Stop bit detection
s
I2C bus busy flag
s
Detection of misplaced start or stop condition
s
Programmable I2C Address detection
s
Transfer problem detection
s
End-of-byte transmission flag
s
Transmitter/Receiver flag
Figure 14.1 I
2C BUS Protocol
14.3 General Description
In addition to receiving and transmitting data, this
interface converts it from serial to parallel format
and vice versa, using either an interrupt or polled
handshake. The interrupts are enabled or disabled
via software. The interface is connected to the I2C
bus by a data pin (SDA) and by a clock pin (SCL).
The interface can be connected both with a
standard I2C bus and a Fast I2C bus. This
selection is made via software.
14.3.1 Mode Selection.
The interface can operate in the following four
modes:
– Slave transmitter/receiver
– Master transmitter/receiver
By default, it operates in slave mode.
The interface automatically switches from slave to
master after it generates a START condition and
from master to slave in case of arbitration loss or a
STOP
generation,
providing
Multi-Master
capability.
14.3.2 Communication Flow.
In Master mode, Communication Flow initiates
data transfer and generates the clock signal. A
serial data transfer always begins with a start
condition and ends with a stop condition. Both start
and stop conditions are generated in master mode
by software.
In Slave mode the interface is capable of
recognizing its own address (7 or 10-bit) and the
General Call address. The General Call address
detection may be enabled or disabled by software.
Data and addresses are transferred as 8-bit bytes,
(MSB first). The first byte(s) follow the start
condition is the address (one in 7-bit mode, two in
10-bit mode), which is always transmitted in
Master mode.A 9th clock pulse follows the 8 clock
cycles of a byte transfer, during which the receiver
must send an acknowledge bit to the transmitter.
Refer to Figure 14.1.
SCL
SDA
12
8
9
MSB
ACK
STOP
START
CONDITION
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