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参数资料
| 型号： | ST52T430K3T6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PQFP32 |
| 封装： | TQFP-32 |
| 文件页数： | 40/88页 |
| 文件大小： | 1162K |
| 代理商： | ST52T430K3T6 |
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ST52T430/E430
45/88
8 A/D CONVERTER
8.1 Introduction
The A/D Converter of ST52x430 is an 8-bit analog
to digital converter with up to 8 analog inputs
offering 8 bit resolution with a total accuracy of 1
LSB and a typical conversion time of 8.2
s with a
20 MHz clock. This period also includes the 5.1
s
of the integral Sample and Hold circuitry, which
minimizes the need for external components and
allows quick sampling of the signal for a minimum
warping effect and Integral conversion error.
Conversion is performed in 82 A/D clock
pulses.
The A/D clock is derived from the clock master.
The maximum A/D clock frequency has to be 10
MHz. When the master clock is higher than 10
MHz it has to be divided by 2 using the SCK bit of
the A/D configuration register REG_CONF 3 (See
The A/D peripheral converts the input voltage with
a process of successive approximations using a
fixed clock frequency derived from the oscillator.
The conversion range is between the analog
VSS and VDD references.
The converter uses a fully differential analog input
configuration for the best noise immunity and
Figure 8.1 A/D Converter Structure
precision performance, along with one separate
supply (VDDA), allowing the best supply noise
rejection.
Up to 8 multiplexed Analog Inputs are available. A
group of signals can be converted sequentially by
simply programming the starting address of the
last analog channel to be converted.
Single
or
continuous
conversion
mode
are
available.
The result of the conversion is stored in an 8-bit
Input Register (from IR 1 to IR 8).
The
A/D
converter
is
controlled
via
the
Configuration Register REG_CONF 3.
A Power-Down programmable bit allows the A/D
converter to be set to a minimum consumption idle
status.
The
ST52x430
Interrupt
Unit
provides
one
maskable channel for the End of Conversion
(EOC).
8.2 Operational Description
The conversion is monotonic, meaning that the
result never decreases if the analog input doesn’t
and never increases if the analog input doesn’t.
If input voltage is greater than or equal to Vdda
(Voltage Reference high) then the result is equal to
FFh (full scale) without an overflow indication.
PB0/AIN0
PB1/AIN1
PB2/AIN2
PB3/AIN3
PB7/PA7/AIN7
PB6/AIN6
PB5/AIN5
PB4/AIN4
ANALOG
MUX
SUCCESSIVE APPROXMATION
A/D CONVERTER
A/D CHANNEL 7
A/D CHANNEL 6
A/D CHANNEL 5
A/D CHANNEL 4
A/D CHANNEL 3
A/D CHANNEL 2
A/D CHANNEL 1
A/D CHANNEL 0
INPUT REGISTER
1 ÷ 8
SAMPLE
HOLD
&
CH2
CH1
CH0
SCK
SEQ
POW
LP
STR
CONFIGURATION REGISTER 3
CONTROL
LOGIC
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