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参数资料
| 型号： | ST52T430K3T6 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 20 MHz, MICROCONTROLLER, PQFP32 |
| 封装： | TQFP-32 |
| 文件页数： | 41/88页 |
| 文件大小： | 1162K |
| 代理商： | ST52T430K3T6 |
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ST52T430/E430
If input voltage is less than VSS (voltage reference
low) then the result is equal to 00h.
The A/D converter is linear and the digital result of
the conversion is provided by the following
formula:
Where Reference Voltage is Vdda - Vss.
The accuracy of the conversion is described in the
Electrical Characteristics Section.
The A/D converter is not affected by the WAIT
mode.
When the MCU enters HALT mode with A/D
converter enabled, the converter is disabled until
HALT mode is terminated and the start-up delay
has elapsed. A stabilization period is also required
before accurate conversions can be performed.
Figure 8.2 Conf. Register (REG_CONF 3)
8.2.1 Operating Modes.
Four main operating modes can be selected by
setting the values of the LP and SEQ bit in the A/D
configuration Register.
One Channel Single Mode
In this mode (SEQ = ‘0’’, LP = ‘0’) the A/D provides
an EOC signal after the end of channel i-th
conversion; then the A/D waits for a new start
event. Channel i-th is identified by the bit CH0,
CH1, CH2.
i.e CH(2:0) = ‘011’ means conversion of channel 3
then stop.
Multiple Channels Single Mode
In this mode (SEQ = ‘1’, LP = ‘0’) the A/D provides
an EOC signal after the end of the channels
sequence conversion identified by the bit CH0,
CH1, CH2; then the A/D waits for a new start event.
i.e. CH(2:0) = ‘011’ means conversion of channels
0,1,2 and 3 then stop.
Digitalr es ult
255inputVoltage
re fe re nce V oltage
------------------------------------------------
=
D 7
D0
CH2 CH1 CH0 SCK SEQ POW
LP STR
REG_CONF 3
START/STOP
CONVERSION MODE SEL.
ON/OFF A/D
CONVERSION MODE SEL.
CLOCK SELECTOR
CHANNELS SEL.
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