参数资料
型号: ST624XB-DBE
厂商: 意法半导体
英文描述: REAL TIME EMULATION DEVELOPMENT TOOLS FOR ST6 MCU FAMILY
中文描述: 实时仿真开发工具,ST6单片机系列
文件页数: 37/74页
文件大小: 733K
代理商: ST624XB-DBE
37/74
ST62T46B/E46B
I/O PORTS
(Cont’d)
4.1.3 LCD alternate functions (combiports)
PC0 to PC7 can also be individually defined as 8
LCD segment output by setting DDRC, ORC and
DRC registers as shown in
Table 12
.
On the contrary with other I/O lines, the reset state
is the LCD output mode. These 8 segment lines are
recognised as S33..S40 by the embedded LCD
controller drive.
4.1.4 SPI alternate functions
PB6/Sin and PB5/Scl pins must be configured as
input through the DDR and OR registers to be
used data in and data clock (Slave mode) for the
SPI. All input modes are available and I/O's can be
read independantly of the SPI at any time.
PB7/Sout must be configured in open drain output
mode to be used as data out for the SPI. In output
mode, the value present on the pin is the port data
register content only if PB7 is defined as push pull
output, while serial transmission is possible only in
open drain mode.
Table 12. PC0-PC7 Combiport Option Selection
Note:
X = Don’t care
Figure 20. Peripheral Interface Configuration of SPI
DDR
0
0
0
0
1
1
OR
0
0
1
1
0
1
DR
0
1
0
1
X
X
Mode
Input
Input
Input
Input
Output
Output
Option
With pull-up, no interrupt
No pull-up, no interrupt
With pull-up and with interrupt
LCD segment (Reset state)
Open-drain output
Push-pull output
PB7/Sout
PB6/Sin
PB5/Scl
PID
OPR
DR
1
MUX0
OUT
IN
SYNCHRONOUS
SERIAL I/O
CLOCK
PID
DR
PID
DR
PP/OD
VR01661F
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