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参数资料
| 型号： | ST62P00CB3/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP16 |
| 封装： | 0.300 INCH, PLASTIC, DIP-16 |
| 文件页数： | 42/100页 |
| 文件大小： | 1713K |
| 代理商： | ST62P00CB3/XXX |
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ST6200C ST6201C ST6203C
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8-BIT TIMER (Cont’d)
8.2.3 Counter/Prescaler Description
Prescaler
The prescaler input is the internal frequency fINT
divided by 12. The prescaler decrements on the
rising edge, depending on the division factor pro-
grammed by the PS[2:0] bits in the TSCR register.
The state of the 7-bit prescaler can be read in the
PSCR register.
When the prescaler reaches 0, it is automatically
reloaded with 7Fh.
Counter
The free running 8-bit downcounter is fed by the
output of the programmable prescaler, and is dec-
remented on every rising edge of the fCOUNTER
clock signal coming from the prescaler.
It is possible to read or write the contents of the
counter on the fly, by reading or writing the timer
counter register (TCR).
When the downcounter reaches 0, it is automati-
cally reloaded with the value 0FFh.
Counter Clock and Prescaler
The counter clock frequency is given by:
fCOUNTER = fPRESCALER / 2
PS[2:0]
where fPRESCALER is:
–fINT/12
The timer input clock feeds the 7-bit programma-
ble prescaler. The prescaler output can be pro-
grammed by selecting one of the 8 available pres-
caler taps using the PS[2:0] bits in the Status/Con-
trol Register (TSCR). Thus the division factor of
the prescaler can be set to 2n (where n equals 0, to
7). See Figure 27.
The clock input is enabled by the PSI (Prescaler
Initialize) bit in the TSCR register. When PSI is re-
set, the counter is frozen and the prescaler is load-
ed with the value 7Fh. When PSI is set, the pres-
caler and the counter run at the rate of the select-
ed clock source.
Counter and Prescaler Initialization
After RESET, the counter and the prescaler are in-
itialized to 0FFh and 7Fh respectively.
The 7-bit prescaler can be initialized to 7Fh by
clearing the PSI bit. Direct write access to the
prescaler is also possible when PSI =1. Then, any
value between 0 and 7Fh can be loaded into it.
The 8-bit counter can be initialized separately by
writing to the TCR register.
8.2.3.1 8-bit Counting and Interrupt Capability
on Counter Underflow
Whatever the division factor defined for the pres-
caler, the Timer Counter works as an 8-bit down-
counter. The input clock frequency is user selecta-
ble using the PS[2:0] bits.
When the downcounter decrements to zero, the
TMZ (Timer Zero) bit in the TSCR is set. If the ETI
(Enable Timer Interrupt) bit in the TSCR is also
set, an interrupt request is generated.
The Timer interrupt can be used to exit the MCU
from WAIT or STOP mode.
The TCR can be written at any time by software to
define a time period ending with an underflow
event, and therefore manage delay or timer func-
tions.
TMZ is set when the downcounter reaches zero;
however, it may also be set by writing 00h in the
TCR register or by setting bit 7 of the TSCR register.
The TMZ bit must be cleared by user software
when servicing the timer interrupt to avoid unde-
sired interrupts when leaving the interrupt service
routine.
Note: A write to the TCR register will predominate
over the 8-bit counter decrement to 00h function,
i.e. if a write and a TCR register decrement to 00h
occur simultaneously, the write will take prece-
dence, and the TMZ bit is not set until the 8-bit
counter underflows again.
8.2.4 Low Power Modes
8.2.5 Interrupts
Mode
Description
WAIT
No effect on timer.
Timer interrupt events cause the device to
exit from WAIT mode.
STOP
Timer registers are frozen.
Interrupt Event
Event
Flag
Enable
Bit
Exit
from
Wait
Exit
from
Stop
Timer Zero
Event
TMZ
ETI
Yes
No
1
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