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参数资料
| 型号： | ST62T03CM6E |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封装： | 0.300 INCH, LEAD FREE, PLASTIC, SOP-16 |
| 文件页数： | 20/100页 |
| 文件大小： | 1440K |
| 代理商： | ST62T03CM6E |
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ST6200C/ST6201C/ST6203C
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6.2 INTERRUPTS
The ST6 core may be interrupted by four maska-
ble interrupt sources, in addition to a Non Maska-
ble Interrupt (NMI) source. The interrupt process-
ing flowchart is shown in Figure 18.
Maskable interrupts must be enabled by setting
the GEN bit in the IOR register. However, even if
they are disabled (GEN bit = 0), interrupt events
are latched and may be processed as soon as the
GEN bit is set.
Each source is associated with a specific Interrupt
Vector, located in Program space (see Table 7). In
the vector location, the user must write a Jump in-
struction to the associated interrupt service rou-
tine.
When an interrupt source generates an interrupt
request, the PC register is loaded with the address
of the interrupt vector, which then causes a Jump
to the relevant interrupt service routine, thus serv-
icing the interrupt.
Interrupt are triggered by events either on external
pins, or from the on-chip peripherals. Several
events can be ORed on the same interrupt vector.
On-chip peripherals have flag registers to deter-
mine which event triggered the interrupt.
Figure 17. Interrupts Block Diagram
NMI
ESB BIT
VDD
LATCH
CLEARED BY H/W
AT START OF VECTOR #0 ROUTINE
VECTOR #0
LES BIT
1
0
LATCH
CLEARED BY H/W
AT START OF
VECTOR #1
VECTOR #2
VECTOR #3
VECTOR #4
LATCH
CLEARED
BY H/W AT START OF
VECTOR #2 ROUTINE
I/O PORT REGISTER
CONFIGURATION
“INPUT WITH INTERRUPT”
I/O PORT REGISTER
CONFIGURATION
“INPUT WITH INTERRUPT”
EXIT FROM
STOP/WAIT
VECTOR #1 ROUTINE
TIMER
A/D CONVERTER *
TMZ BIT
ETI BIT
EAI BIT
EOC BIT
GEN BIT
PB0..PB1
PA1..PA3
(TSCR REGISTER)
(ADCR REGISTER)
(IOR REGISTER)
PB3
PB5..PB7
* Depending on device. See device summary on page 1.
1
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