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参数资料
型号： ST62T03CM6E
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO16
封装： 0.300 INCH, LEAD FREE, PLASTIC, SOP-16
文件页数： 48/100页
文件大小： 1440K
代理商： ST62T03CM6E
ST6200C/ST6201C/ST6203C
51/100
A/D CONVERTER (Cont’d)
9.3.5 Low Power Modes
Note: The A/D converter may be disabled by clear-
ing the PDS bit. This feature allows reduced power
consumption when no conversion is needed.
9.3.6 Interrupts
Note: The EOC bit is cleared only when a new
conversion is started (it cannot be cleared by writ-
ing 0). To avoid generating further EOC interrupt,
the EAI bit has to be cleared within the ADC inter-
rupt subroutine.
9.3.7 Register Description
A/D CONVERTER CONTROL REGISTER (AD-
CR)
Address: 0D1h - Read/Write (Bit 6 Read Only, Bit
5 Write Only)
Reset value: 0100 0000 (40h)
Bit 7 = EAI Enable A/D Interrupt.
0: ADC interrupt disabled
1: ADC interrupt enabled
Bit 6 = EOC End of conversion. Read Only
When a conversion has been completed, this bit is
set by hardware and an interrupt request is gener-
ated if the EAI bit is set. The EOC bit is automati-
cally cleared when the STA bit is set. Data in the
data conversion register are valid only when this
bit is set to “1”.
0: Conversion is not complete
1: Conversion can be read from the ADR register
Bit 5 = STA: Start of Conversion. Write Only.
0: No effect
1: Start conversion
Note: Setting this bit automatically clears the EOC
bit. If the bit is set again when a conversion is in
progress, the present conversion is stopped and a
new one will take place. This bit is write only, any
attempt to read it will show a logical zero.
Bit 4 = PDS Power Down Selection.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 3 = ADCR3 Reserved, must be cleared.
Bit 2 = OSCOFF Main Oscillator off.
0: Main Oscillator enabled
1: Main Oscillator disabled
Note: This bit does not apply to the ADC peripher-
al but to the main clock system. Refer to the Clock
System section.
Bits 1:0 = ADCR[1:0] Reserved, must be cleared.
A/D CONVERTER DATA REGISTER (ADR)
Address: 0D0h - Read only
Reset value: xxxx xxxx (xxh)
Bits 7:0 = ADR[7:0]: 8 Bit A/D Conversion Result.
Table 14. ADC Register Map and Reset Values
Mode
Description
WAIT
No effect on A/D Converter. ADC interrupts
cause the device to exit from Wait mode.
STOP
A/D Converter disabled.
Interrupt Event
Event
Flag
Enable
Bit
Exit
from
Wait
Exit
from
Stop
End of Conver-
sion
EOC
EAI
Yes
No
70
EAI
EOC
STA
PDS
ADCR
3
OSC
OFF
ADCR
1
ADCR
0
70
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
ADR1
ADR0
Address
(Hex.)
Register
Label
7654
3210
0D0h
ADR
Reset Value
ADR7
0
ADR6
0
ADR5
0
ADR4
0
ADR3
0
ADR2
0
ADR1
0
ADR0
0
0D1h
ADCR
Reset Value
EAI
0
EOC
1
STA
0
PDS
0
ADCR3
0
OSCOFF
0
ADCR1
0
ADCR0
0
1
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