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参数资料
| 型号： | ST6397 |
| 厂商： | 意法半导体 |
| 英文描述： | 8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| 中文描述： | 8位微控制器HCMOS电视频率合成带OSD |
| 文件页数： | 29/68页 |
| 文件大小： | 560K |
| 代理商： | ST6397 |
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INPUT/OUTPUT PORTS
The ST639x microcontrollers use three standard
I/Oports (A,B,C)withup to eightpinson each port;
refer to the devicepin configurationsto see which
pins areavailable.
Each linecan beindividuallyprogrammed either in
the input mode or the output mode as follows by
software.
-
Output
-
Input with on-chip pull-up resistor (selected by
software)
-
Input withouton-chip pull-up resistor (selected
by software)
Note: pins with 12V open-drain capability do not
have pull-upresistors.
In output mode the following hardware configura-
tions are available:
-
Open-drain output 12V (PA4-PA7,PC4-PC7)
-
Open-drain output 5V (PC0-PC3)
-
Push-pull output (PA0-PA3,PB0-PB6)
The linesareorganizedinthree ports(portA,B,C).
The ports occupy 6 registers in the data space.
Each bitof theseregistersis associatedwith apar-
ticular line (for instance, the bits 0 of the Port A
Data and Direction registers are associated with
the PA0 line of PortA).
There arethree Data registers (DRA, DRB, DRC),
that areusedtoread thevoltage level valuesofthe
lines programmedinthe inputmode, or towritethe
logic value of the signal to be output on the lines
configured inthe output mode.The port DataReg-
isters can be read togetthe effectivelogiclevelsof
the pins, but they can be also written by the user
software, in conjunction with the related Data Di-
rection Register, to select the different input mode
options. Single-bit operations on I/O registers (bit
set/resetinstructions)are possible but care is nec-
essary because reading in input mode is made
from I/Opins and therefore mightbe influenced by
the external load, while writing will directly affect
the Port data register causing an undesired
changes of the inputconfiguration.The threeData
Direction registers (DDRA, DDRB, DDRC) allow
the selection of the direction of each pin (input or
output).
All the I/O registers can be read or written as any
other RAM location of the data space, so no extra
RAM cell is needed for port data storing and ma-
nipulation. During the initialization of the MCU, all
the I/O registers are cleared and the input mode
with pull-upis selectedon all the pinsthusavoiding
pin conflicts(with theexceptionofPC2that issetin
output mode and is sethigh ie. highimpedance).
Details ofI/O Ports
When programmed asan inputapull-upresistor(if
available) can be switched active under program
control. When programmed as an output the I/O
port willoperate either inthepush-pullmode orthe
open-drainmode according to the hardware fixed
configuration asspecified below.
Port A.
PA0-PA3are available as push-pullwhen
outputs. PA4-PA7are available as open-drain (no
push-pull programmability) capable of withstand-
ing 12V (no resistive pull-up in input mode). PA6-
PA7 hasbeen speciallydesignedforhigher driving
capability and are able to sink 25mA with a maxi-
mum V
OL
of1V.
Port B.
All lines are configured as push-pullwhen
outputs.
Port C.
PC0-PC3 are availableas open-drain ca-
pable ofwithstanding a maximum V
DD
+0.3V.PC4-
PC7 are available as open-drain capable of
withstanding 12V (no resistive pull-up in input
mode). Some lines are also usedas I/O buffersfor
signals comingfrom the on-chip SPI.
In this case the final signal on the output pin is
equivalent to a wired AND with the programmed
data output.
If the user needs to use the serial peripheral, the
I/O line should be set in output mode while the
open-drain configuration is hardware fixed; the
corresponding data bit must set to one. If the
latchedinterrupt functionsareused(IRIN, PWRIN)
then the corresponding pins shouldbe set to input
mode.
On ST639x the I/O pins with double or special
functions are:
-
PC0/SCL (connected to theSPI clock signal)
-
PC1/SDA(connected to the SPI data signal)
-
PC3/SEN(connected totheSPIenable signal)
-
PC4/PWRIN (connected to the PWRIN inter-
rupt latch)
-
PC6/IRIN (connected to the IRIN interrupt
latch)
All the Port A,B and C I/Olines have Schmitt-trig-
ger input configuration with a typical hysteresis of
1V.
ST6391,92,93,95,97,99
25/64
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ST6397B1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6399 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST6399B1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY SYNTHESIS WITH OSD |
| ST63E126D1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY & VOLTAGE SYNTHESIS WITH OSD |
| ST63E140D1 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:8-BIT HCMOS MCUs FOR TV FREQUENCY & VOLTAGE SYNTHESIS WITH OSD |
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