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参数资料
| 型号： | ST72121J2T6/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | PLASTIC, TQFP-44 |
| 文件页数： | 20/87页 |
| 文件大小： | 1365K |
| 代理商： | ST72121J2T6/XXX |
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ST72121
I/O PORTS (Cont’d)
4.1.3 Register Description
4.1.3.1 Data registers
Port A Data Register (PADR)
Port B Data Register (PBDR)
Port C Data Register (PCDR)
Port D Data Register (PDDR)
Port E Data Register (PEDR)
Port F Data Register (PFDR)
Read /Write
Reset Value: 0000 0000 (00h)
Bit 7:0 = D7-D0
Data Register 8 bits.
The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken in account
even if the pin is configured as an input. Reading
the DR register returns either the DR register latch
content (pin configured as output) or the digital val-
ue applied to the I/O pin (pin configured as input).
4.1.3.2 Data direction registers
Port A Data Direction Register (PADDR)
Port B Data Direction Register (PBDDR)
Port C Data Direction Register (PCDDR)
Port D Data Direction Register (PDDDR)
Port E Data Direction Register (PEDDR)
Port F Data Direction Register (PFDDR)
Read/Write
Reset Value: 0000 0000 (00h) (input mode)
Bit 7:0 = DD7-DD0
Data Direction Register 8 bits.
The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.
0: Input mode
1: Output mode
4.1.3.3 Option registers
Port A Option Register (PAOR)
Port B Option Register (PBOR)
Port C Option Register (PBOR)
Port D Option Register (PBOR)
Port E Option Register (PBOR)
Port F Option Register (PFOR)
Read/Write
Reset Value: see Register Memory Map Table 3
Bit 7:0 = O7-O0
Option Register 8 bits.
The OR register allow to distinguish in input mode
if the interrupt capability or the floating configura-
tion is selected.
In output mode it select push-pull or open-drain
capability.
Each bit is set and cleared by software.
Input mode:
0: floating input
1: input pull-up with interrupt
Output mode:
0: open-drain configuration
1: push-pull configuration
70
D7
D6
D5
D4
D3
D2
D1
D0
70
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
70
O7
O6
O5
O4
O3
O2
O1
O0
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