参数资料
型号: ST72121J2T6/XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44
封装: PLASTIC, TQFP-44
文件页数: 29/87页
文件大小: 1365K
代理商: ST72121J2T6/XXX
35/87
ST72121
16-BIT TIMER (Cont’d)
4.3.3.3 Input Capture
In this section, the index,
i, may be 1 or 2.
The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAP
i pin (see figure 5).
IC
i Rregister is a read-only register.
The active transition is software programmable
through the IEDG
i bitofthe ControlRegister (CRi).
Timing resolution is one count of the free running
counter: (
fCPU/(CC1.CC0)).
Procedure
To use the input capture function select the follow-
inginthe CR2 register:
– Select the timer clock (CC1-CC0) (see Table
14).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit.
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture.
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit.
When an input capture occurs:
–ICF
i bit is set.
–The IC
iR register contains the value of the free
runningcounter on theactivetransitiononthe
ICAP
i pin (see Figure 25).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request is
done in two steps:
1. Reading the SR register while the ICF
i bit is set.
2. An access (read or write) to the IC
iLR register.
Note: After reading the IC
iHR register, transfer of
input capture data is inhibited until the IC
iLR regis-
ter is also read.
The IC
iR register always contains the free running
counter value which corresponds to the most re-
cent input capture.
During HALT mode, if at least one valid input cap-
ture edge occurs on the ICAP
i pin, the input cap-
ture detection circuitry is armed. This does not set
any timer flags, and does not “wake-up” the MCU.
If the MCU is awoken by an interrupt, the input
capture flag will become active, and data corre-
sponding to the first valid edge during HALT mode
will be present.
MS Byte
LS Byte
ICiR
IC
iHR
IC
iLR
35
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