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| 型号： | ST72121J4T1/XXX |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQFP44 |
| 封装： | PLASTIC, TQFP-44 |
| 文件页数： | 31/87页 |
| 文件大小： | 1365K |
| 代理商： | ST72121J4T1/XXX |
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ST72121
16-BIT TIMER (Cont’d)
4.3.3.4 Output Compare
In this section, the index,
i, may be 1 or 2.
This function can be used to control an output
waveform or indicating when a period of time has
elapsed.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OCIE bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the free run-
ning counter each timer clock cycle.
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OCiR value to 8000h.
Timing resolution is one count of the free running
counter: (
fCPU/(CC1.CC0)).
Procedure
To use the output compare function, select the fol-
lowing in the CR2 register:
–Set the OC
iE bit if an output is needed then the
OCMP
i pin is dedicated to the output compare i
function.
– Select the timer clock (CC1-CC0) (see Table
14).
And select the following in the CR1 register:
– Select the OLVL
i bit to applied to the OCMPi pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found:
–OCF
i bit is set.
–The OCMP
i pin takes OLVLi bit value (OCMPi
pin latch is forced low during reset and stays low
until valid compares change it to a high level).
– A timer interrupt is generated if the OCIE bit is
set in the CR2 register and the I bit is cleared in
the CC register (CC).
Clearing the output compare interrupt request is
done by:
1. Reading the SR register while the OCF
i bit is
set.
2. An access (read or write) to the OC
iLR register.
Note: After a processor write cycle to the OC
iHR
register, the output compare function is inhibited
until the OC
iLR register is also written.
If the OC
iE bit is not set, the OCMPi pin is a gen-
eral I/O port and the OLVL
i bit will not appear
when a match is found but an interrupt could be
generated if the OCIE bit is set.
The value in the 16-bit OCiR register and the OLV
i
bit should be changed after each successful com-
parison in order to control an output waveform or
establish a new elapsed timeout.
When the clock is divided by 2, OCF
i and OCMPi
are set while the counter value equals the OC
iR
register value (see Figure 27, on page 38). This
behaviour is the same in OPM or PWM mode.
When the clock is divided by 4, 8 or in external
clock mode , OCF
i and OCMPi are set while the
counter value equals the OC
iR register value plus
1 (see Figure 28, on page 38).
The OCiR register value required for a specific tim-
ingapplication canbe calculatedusing thefollow-
ing formula:
Where:
t
= Desired output compare period (in
seconds)
fCPU
= Internal clock frequency
tPRESC = Timer clock prescaler (CC1-CC0 bits,
see Table 14)
The following procedure is recommended to pre-
vent the OCF
i bit from being set between the time
it is read and the write to the OCiR register:
– Write to the OC
iHR register (further compares
are inhibited).
– Read the SR register (first step of the clearance
of the OCF
i bit, which may be already set).
– Write to the OC
iLR register (enables the output
compare function and clears the OCF
i bit).
MS Byte
LS Byte
OC
iROCiHR
OC
iLR
OCiR=
t * fCPU
tPRESC
37
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相关代理商/技术参数 |
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