参数资料
型号: ST72F324K2
英文描述: 8-BIT MCU WITH NESTED INTERRUPTS. FLASH. 10-BIT ADC. 4 TIMERS. SPI. SCI INTERFACE
中文描述: 8位微控制器嵌套中断。闪光。 10位ADC。 4定时器。的SPI。 SCI接口
文件页数: 50/161页
文件大小: 2070K
代理商: ST72F324K2
ST72324
143/161
ADC CHARACTERISTICS (Cont’d)
12.12.1 Analog Power Supply and Reference
Pins
Depending on the MCU pin count, the package
may feature separate VAREF and VSSA analog
power supply pins. These pins supply power to the
A/D converter cell and function as the high and low
reference voltages for the conversion. In some
packages, VAREF and VSSA pins are not available
(refer to Table 1). In this case the analog supply
and reference pads are internally bonded to the
VDD and VSS pins.
Separation of the digital and analog power pins al-
low board designers to improve A/D performance.
Conversion accuracy can be impacted by voltage
drops and noise in the event of heavily loaded or
badly decoupled power supply lines (see Section
12.12.2 General PCB Design Guidelines
To obtain best results, some general design and
layout rules should be followed when designing
the application PCB to shield the noise-sensitive,
analog physical interface from noise-generating
CMOS logic signals.
– Use separate digital and analog planes. The an-
alog ground plane should be connected to the
digital ground plane via a single point on the
PCB.
– Filter power to the analog power planes. It is rec-
ommended to connect capacitors, with good high
frequency characteristics, between the power
and ground lines, placing 0.1F and optionally, if
needed 10pF capacitors as close as possible to
the ST7 power supply pins and a 1 to 10F ca-
pacitor close to the power source (see Figure
– The analog and digital power supplies should be
connected in a star nework. Do not use a resis-
tor, as VAREF is used as a reference voltage by
the A/D converter and any resistance would
cause a voltage drop and a loss of accuracy.
– Properly place components and route the signal
traces on the PCB to shield the analog inputs.
Analog signals paths should run over the analog
ground plane and be as short as possible. Isolate
analog signals from digital signals that may
switch while the analog inputs are being sampled
by the A/D converter. Do not toggle digital out-
puts on the same I/O port as the A/D input being
converted.
Figure 93. Power Supply Filtering
VSS
VDD
0.1
F
10pF
VDD
ST72XXX
VAREF
VSSA
POWER
SUPPLY
SOURCE
ST7
DIGITAL NOISE
FILTERING
EXTERNAL
NOISE
FILTERING
1 to 10
F
0.1
F
10pF
(if needed)
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