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参数资料
型号： ST72F324K2B3
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDIP32
封装： 0.400 INCH, SHRINK, PLASTIC, DIP-32
文件页数： 78/156页
文件大小： 1012K
代理商： ST72F324K2B3
ST72324J/K
28/156
SYSTEM INTEGRITY MANAGEMENT (Cont’d)
6.4.3 Clock Security System (CSS)
The Clock Security System (CSS) protects the
ST7 against main clock problems. To allow the in-
tegration of the security features in the applica-
tions, it is based on a clock filter control and an In-
ternal safe oscillator. The CSS can be enabled or
disabled by option byte.
6.4.3.1 Clock Filter Control
The clock filter is based on a clock frequency limi-
tation function.
This filter function is able to detect and filter high
frequency spikes on the ST7 main clock.
If the oscillator is not working properly (e.g. work-
ing at a harmonic frequency of the resonator), the
current active oscillator clock can be totally fil-
tered, and then no clock signal is available for the
ST7 from this oscillator anymore. If the original
clock source recovers, the filtering is stopped au-
tomatically and the oscillator supplies the ST7
clock.
6.4.3.2 Safe Oscillator Control
The safe oscillator of the CSS block is a low fre-
quency back-up clock source (see Figure 17).
If the clock signal disappears (due to a broken or
disconnected resonator...) during a safe oscillator
period, the safe oscillator delivers a low frequency
clock signal which allows the ST7 to perform some
rescue operations.
Automatically, the ST7 clock source switches back
from the safe oscillator if the original clock source
recovers.
Limitation detection
The automatic safe oscillator selection is notified
by hardware setting the CSSD bit of the SICSR
register. An interrupt can be generated if the CS-
SIE bit has been previously set.
These two bits are described in the SICSR register
description.
6.4.4 Low Power Modes
6.4.4.1 Interrupts
The CSS or AVD interrupt events generate an in-
terrupt if the corresponding Enable Control Bit
(CSSIE or AVDIE) is set and the interrupt mask in
the CC register is reset (RIM instruction).
Note 1: This interrupt allows to exit from active-
halt mode.
Figure 17. Clock Filter Function and Safe Oscillator Function
Mode
Description
WAIT
No effect on SI. CSS and AVD interrupts
cause the device to exit from Wait mode.
HALT
The CRSR register is frozen.
The CSS (including the safe oscillator) is
disabled until HALT mode is exited. The
previous CSS configuration resumes when
the MCU is woken up by an interrupt with
“exit from HALT mode” capability or from
the counter reset value when the MCU is
woken up by a RESET. The AVD remains
active, and an AVD interrupt can be used to
exit from Halt mode.
Interrupt Event
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
CSS event detection
(safe oscillator acti-
vated as main clock)
CSSD
CSSIE
Yes
No 1)
AVD event
AVDF
AVDIE
Yes
fOSC/2
fCPU
fOSC/2
fCPU
fSFOSC
SAFE
OSCILLATOR
FUNCTION
CLOCK
FILTER
FUNCTION
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相关代理商/技术参数
参数描述
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ST72F324K2T3 制造商:STMicroelectronics 功能描述:
ST72F324K2T3TR 制造商:STMicroelectronics 功能描述:
ST72F324K2T6 功能描述:8位微控制器 -MCU Flash 8K SPI/SCI RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
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