参数资料
型号: ST72F345N4H6
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PBGA56
封装: 6 X 6 MM, LEAD FREE, TFBGA-56
文件页数: 40/190页
文件大小: 3666K
代理商: ST72F345N4H6
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页当前第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页第154页第155页第156页第157页第158页第159页第160页第161页第162页第163页第164页第165页第166页第167页第168页第169页第170页第171页第172页第173页第174页第175页第176页第177页第178页第179页第180页第181页第182页第183页第184页第185页第186页第187页第188页第189页第190页
ST72340, ST72344, ST72345
134/190
Notes:
– The Status Register has to be read to clear the
event flag associated with the interrupt
– An interrupt will be generated only if the interrupt
enable bit is set in the Control Register
– Slaves 1 and 2 have a common interrupt and the
Slave 3 has a separate interrupt.
– At the end of write operation, I2C3S is temporar-
ily disabled by hardware by setting BusyW bit in
CR2. The byte count register, status register and
current address register should be saved before
resetting BusyW bit.
.
11.7.5.1 Slave Reception (Write operations)
Byte Write: The Slave address is followed by an
8-bit byte address. Upon receipt of this address an
acknowledge is generated, address is moved into
the current address register and the 8 bit data is
clocked in. Once the data is shifted in, a DMA
request is generated and the data is written in the
RAM. The addressing device will terminate the
write sequence with a stop condition. Refer to
Page Write: A page write is initiated in similar way
to a byte write, but the addressing device does not
send a stop condition after the first data byte. The
page length is programmed using bits 7:6 (PL[1:0])
in the Control Register1.
The current address register value is incremented
by one every time a byte is written. When this
address reaches the page boundary, the next byte
will be written at the beginning of the same page.
Refer to Figure 76.
11.7.5.2 Slave Transmission (Read Operations)
Current Address Read: The current address
register maintains the last address accessed
during the last read or write operation incremented
by one.
During this operation the I2C slave reads the data
pointed by the current address register. Refer to
Random Read: Random read requires a dummy
byte write sequence to load in the byte address.
The addressing device then generates restart
condition and resends the device address similar
to current address read with the read/write bit high.
Refer to Figure 78. Some types of I2C masters
perform a dummy write with a stop condition and
then a current address read.
In either case, the slave generates a DMA request,
sends an acknowledge and serially clocks out the
data.
When the memory address limit is reached the
current address will roll over and the random read
will continue till the addressing master sends a
stop condition.
Sequential Read: Sequential reads are initiated
by either a current address read or a random
address
read.
After
the
addressing
master
receives the data byte it responds with an
acknowledge. As long as the slave receives an
acknowledge it will continue to increment the
current address register and clock out sequential
data bytes.
When the memory address limit is reached the
current address will roll over and the sequential
read will continue till the addressing master sends
a stop condition. Refer to Figure 80
11.7.5.3 Combined Format:
If a master wants to continue communication
either with another slave or by changing the
direction of transfer then the master would
generate a restart and provide a different slave
address or the same slave address with the R/W
bit reversed. Refer to Figure 81.
相关PDF资料
PDF描述
ST72F60E1M1 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO24
ST72F60K2DIE1 8-BIT, MROM, 8 MHz, MICROCONTROLLER, UUC
ST72F60K2DIE6 8-BIT, MROM, 8 MHz, MICROCONTROLLER, UUC
ST72F651AR6T1 8-BIT, FLASH, MICROCONTROLLER, PQFP64
ST72P60E2M1 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO24
相关代理商/技术参数
参数描述
ST72F34X-SK/RAIS 功能描述:开发板和工具包 - 其他处理器 DEV. KIT RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压:
ST72F361AR6T3 功能描述:8位微控制器 -MCU 8B MCU with Flash RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F361AR6T6 功能描述:8位微控制器 -MCU 8-bit MCU with Flash or ROM 10-bit ADC RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F361AR6TA 功能描述:8位微控制器 -MCU 8-bit MCU Flash RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT
ST72F361AR6TAE 功能描述:8位微控制器 -MCU 8B MCU with Flash RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT