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参数资料
| 型号： | ST72F611F1M1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | 0.300 INCH, PLASTIC, SOIC-20 |
| 文件页数： | 27/71页 |
| 文件大小： | 403K |
| 代理商： | ST72F611F1M1 |
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ST7261
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WATCHDOG TIMER (Cont’d)
9.1.4 Software Watchdog Option
If Software Watchdog is selected by option byte,
the watchdog is disabled following a reset. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
9.1.5 Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.
9.1.6 Low Power Modes
WAIT Instruction
No effect on Watchdog.
HALT Instruction
Halt mode can be used when the watchdog is en-
abled. When the oscillator is stopped, the WDG
stops counting and is no longer able to generate a
reset until the microcontroller receives an external
interrupt or a reset.
If an external interrupt is received, the WDG re-
starts counting after 514 CPU clocks. In the case
of the Software Watchdog option, if a reset is gen-
erated, the WDG is disabled (reset state).
Recommendations
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– Before executing the HALT instruction, refresh
the WDG counter, to avoid an unexpected WDG
reset immediately after waking up the microcon-
troller.
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as Input before executing the HALT instruction.
The main reason for this is that the I/O may be
wrongly configured due to external interference
or by an unforeseen logical condition.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– As the HALT instruction clears the I bit in the CC
register to allow interrupts, the user may choose
to clear all pending interrupt bits before execut-
ing the HALT instruction. This avoids entering
other peripheral interrupt routines after executing
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
9.1.7 Interrupts
None.
9.1.8 Register Description
CONTROL REGISTER (CR)
Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = WDGA
Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bit 6:0 = T[6:0]
7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
70
WDGA
T6
T5
T4
T3
T2
T1
T0
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