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参数资料
| 型号： | ST72F611F1M1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO20 |
| 封装： | 0.300 INCH, PLASTIC, SOIC-20 |
| 文件页数： | 35/71页 |
| 文件大小： | 403K |
| 代理商： | ST72F611F1M1 |
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ST7261
40/71
USB INTERFACE (Cont’d)
PID REGISTER (PIDR)
Read only
Reset Value: xx00 0000 (x0h)
Bits 7:6 = TP[3:2]
Token PID bits 3 & 2.
USB token PIDs are encoded in four bits. TP[3:2]
correspond to the variable token PID bits 3 & 2.
Note: PID bits 1 & 0 have a fixed value of 01.
When a CTR interrupt occurs (see register ISTR)
the software should read the TP3 and TP2 bits to
retrieve the PID name of the token received.
The USB standard defines TP bits as:
Bits 5:3 Reserved. Forced by hardware to 0.
Bit 2 = RX_SEZ
Received single-ended zero
This bit indicates the status of the RX_SEZ trans-
ceiver output.
0: No SE0 (single-ended zero) state
1: USB lines are in SE0 (single-ended zero) state
Bit 1 = RXD
Received data
0: No K-state
1: USB lines are in K-state
This bit indicates the status of the RXD transceiver
output (differential receiver output).
Note: If the environment is noisy, the RX_SEZ and
RXD bits can be used to secure the application. By
interpreting the status, software can distinguish a
valid End Suspend event from a spurious wake-up
due to noise on the external USB line. A valid End
Suspend is followed by a Resume or Reset se-
quence. A Resume is indicated by RXD=1, a Re-
set is indicated by RX_SEZ=1.
Bit 0 = Reserved. Forced by hardware to 0.
INTERRUPT STATUS REGISTER (ISTR)
Read / Write
Reset Value: 0000 0000 (00h)
When an interrupt occurs these bits are set by
hardware. Software must read them to determine
the interrupt type and clear them after servicing.
Note: These bits cannot be set by software.
Bit 7 = SUSP
Suspend mode request.
This bit is set by hardware when a constant idle
state is present on the bus line for more than 3 ms,
indicating a suspend mode request from the USB
bus. The suspend request check is active immedi-
ately after each USB reset event and its disabled
by hardware when suspend mode is forced
(FSUSP bit of CTLR register) until the end of
resume sequence.
Bit 6 = DOVR
DMA over/underrun.
This bit is set by hardware if the ST7 processor
can’t answer a DMA request in time.
0: No over/underrun detected
1: Over/underrun detected
Bit 5 = CTR
Correct Transfer. This bit is set by
hardware when a correct transfer operation is per-
formed. The type of transfer can be determined by
looking at bits TP3-TP2 in register PIDR. The End-
point on which the transfer was made is identified
by bits EP1-EP0 in register IDR.
0: No Correct Transfer detected
1: Correct Transfer detected
Note: A transfer where the device sent a NAK or
STALL handshake is considered not correct (the
host only sends ACK handshakes). A transfer is
considered correct if there are no errors in the PID
and CRC fields, if the DATA0/DATA1 PID is sent
as expected, if there were no data overruns, bit
stuffing or framing errors.
Bit 4 = ERR
Error.
This bit is set by hardware whenever one of the er-
rors listed below has occurred:
0: No error detected
1: Timeout, CRC, bit stuffing or nonstandard
framing error detected
70
TP3
TP2
0
RX_
SEZ
RXD
0
TP3
TP2
PID Name
00
OUT
10
IN
1
SETUP
70
SUSP
DOVR
CTR
ERR
IOVR
ESUSP
RESET
SOF
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