
ST7L34, ST7L35, ST7L38, ST7L39
I/O ports
Doc ID 11928 Rev 7
10
I/O ports
10.1
Introduction
The I/O ports allow data transfer. An I/O port contains up to eight pins. Each pin can be
programmed independently either as a digital input or digital output. In addition, specific pins
may have several other functions. These functions can include external interrupt, alternate
signal input/output for on-chip peripherals or analog input.
10.2
Functional description
A data register (DR) and a data direction register (DDR) are always associated with each
port. The option register (OR), which allows input/output options, may or may not be
implemented. The following description takes into account the OR register. Refer
information.
An I/O pin is programmed using the corresponding bits in the DDR, DR and OR registers:
Bit x corresponding to pin x of the port.
10.2.1
Input modes
Clearing the DDRx bit selects input mode. In this mode, reading its DR bit returns the digital
value from that I/O pin.
If an OR bit is available, different input modes can be configured by software: Floating or
Note:
1
Writing to the DR modifies the latch value but does not change the state of the input pin.
2
Do not use read/modify/write instructions (BSET/BRES) to modify the DR register.
External interrupt function
Depending on the device, setting the ORx bit while in input mode can configure an I/O as an
input with interrupt. In this configuration, a signal edge or level input on the I/O generates an
interrupt request via the corresponding interrupt vector (eix).Falling or rising edge sensitivity
is programmed independently for each interrupt vector. The external interrupt control
register (EICR) or the miscellaneous register controls this sensitivity, depending on the
device.
Each external interrupt vector is linked to a dedicated group of I/O port pins (see pinout
interrupt pins on the same interrupt vector are selected simultaneously, they are logically
combined. For this reason, if one of the interrupt pins is tied low, it may mask the others.
External interrupts are hardware interrupts. Fetching the corresponding interrupt vector
automatically clears the request latch. Changing the sensitivity bits clears any pending
interrupts.