
On-chip peripherals
ST7L34, ST7L35, ST7L38, ST7L39
Doc ID 11928 Rev 7
Table 64.
SCISR register description
Bit
Bit name
Function
7TDRE
Transmit data register empty
This bit is set by hardware when the content of the TDR register has
been transferred into the shift register. An interrupt is generated if the
TIE bit = 1 in the SCICR2 register. It is cleared by a software
sequence (an access to the SCISR register followed by a write to the
SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
6TC
Transmission complete
This bit is set by hardware when transmission of a character
containing data is complete. An interrupt is generated if TCIE = 1 in
the SCICR2 register. It is cleared by a software sequence (an access
to the SCISR register followed by a write to the SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Note: TC is not set after the transmission of a preamble or a break.
5
RDRF
Received data ready flag
This bit is set by hardware when the content of the RDR register has
been transferred to the SCIDR register. An interrupt is generated if
RIE = 1 in the SCICR2 register. It is cleared by a software sequence
(an access to the SCISR register followed by a read to the SCIDR
register).
0: Data are not received
1: Received data are ready to be read
4IDLE
Idle line detect
This bit is set by hardware when an idle line is detected. An interrupt
is generated if the ILIE = 1 in the SCICR2 register. It is cleared by a
software sequence (an access to the SCISR register followed by a
read to the SCIDR register).
0: No idle line is detected
1: Idle line is detected
Note: The IDLE bit is not set again until the RDRF bit is set (i.e. a new
idle line occurs).
3OR
Overrun error
This bit is set by hardware when the word currently being received in
the shift register is ready to be transferred into the RDR register
while RDRF = 1. An interrupt is generated if RIE = 1 in the SCICR2
register. It is cleared by a software sequence (an access to the
SCISR register followed by a read to the SCIDR register).
0: No overrun error
1: Overrun error is detected
Note: When the IDLE bit is set the RDR register content is not lost but
the shift register is overwritten.