参数资料
型号: ST7FLCD1G9M1
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PDSO28
封装: ROHS COMPLIANT, SO-28
文件页数: 76/96页
文件大小: 846K
代理商: ST7FLCD1G9M1
8-bit Timer (TIMA)
ST7FLCD1
13.4
Register Description
TIMER A CONTROL STATUS REGISTER (TIMCSRA)
Read/Write
Reset Value: (00h)
Bits [7:6] = TB[1:0] Time Base period selection
These bits are set and cleared by software.
00 Time base period = tTIMER (256 s @ 8 MHz)
01 Time base period = tTIMER x 8 (2048 s @ 8 MHz)
10 Time base period = tTIMER x 64 (16384 s @ 8 MHz)
11 Reserved
Bit 5 = OVF Timer Overflow Flag.
This bit is set by hardware. An interrupt is generated if OVFE = 1. It must be cleared by reading the
TIMCSRA register.
0
No timer overflow.
1
The free-running downcounter reached 00h.
Bit 4 = OVFE Timer Overflow Interrupt Enable.
This bit is set and cleared by software.
0
Interrupt disabled
1
Interrupt enabled
Bit 3 = TAR Timer Auto-Reload
This bit is set and cleared by software.
0
One-shot mode. The counter restarts after a write in the TIMCPRA register.
1
Auto-Reload mode. The counter is reloaded automatically by the TIMCPRA register after the
downcounter reaches 00h.
Bits [2:1] = BUZ[1:0] Buzzer tone selection
These bits are set and cleared by software.
00 Time base frequency = fTIMER/16 (244 Hz @ 8 MHz)
01 Time base frequency = fTIMER/8 (488 Hz @ 8 MHz)
10 Time base frequency = fTIMER/4 (976 Hz@ 8 MHz)
11 Time base frequency = fTIMER/2 (1.95 kHz @ 8 MHz)
Table 27: Timer Controller Register Map
Address
Reset
Register
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
000Dh
00h
R/W
TIMCSRA
TB1
TB0
OVF
OVFE
TAR
BUZ1
BUZ0
BUZE
000Eh
00h
R/W
TIMCPRA
PR7
PR6
PR5
PR4
PR3
PR2
PR1
PR0
765
432
10
TB1
TB0
OVF
OVFE
TAR
BUZ1
BUZ0
BUZE
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