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| 型号： | ST7PLITE15BF0B3 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP20 |
| 封装： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-20 |
| 文件页数： | 115/159页 |
| 文件大小： | 2855K |
| 代理商： | ST7PLITE15BF0B3 |
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ST7LITE1xB
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DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
11.2.3 Functional Description
11.2.3.1 PWM Mode
This mode allows up to four Pulse Width Modulat-
ed signals to be generated on the PWMx output
pins.
PWM Frequency
The four PWM signals can have the same fre-
quency (fPWM) or can have two different frequen-
cies. This is selected by the ENCNTR2 bit which
enables single timer or dual timer mode (see Fig-
ure 1 and Figure 2).
The frequency is controlled by the counter period
and the ATR register value. In dual timer mode,
PWM2 and PWM3 can be generated with a differ-
ent frequency controlled by CNTR2 and ATR2.
fPWM = fCOUNTER / (4096 - ATR)
Following the above formula,
– If fCOUNTER is 4 MHz, the maximum value of
fPWM is 2 MHz (ATR register value = 4094), the
minimum value is 1 kHz (ATR register value = 0).
– If fCOUNTER is 32 MHz, the maximum value of
fPWM is 8 MHz (ATR register value = 4092), the
minimum value is 8 kHz (ATR register value = 0).
Notes:
1. The maximum value of ATR is 4094 because it
must be lower than the DC4R value which must be
4095 in this case.
2. To update the DCRx registers at 32 MHz, the
following precautions must be taken:
– if the PWM frequency is < 1 MHz and the TRANx
bit is set asynchronously, it should be set twice
after a write to the DCRx registers.
– if the PWM frequency is > 1 MHz, the TRANx bit
should be set along with FORCEx bit with the
same instruction (use a load instruction and not
2 bset instructions).
Duty Cycle
The duty cycle is selected by programming the
DCRx registers. These are preload registers. The
DCRx values are transferred in Active duty cycle
registers after an overflow event if the correspond-
ing transfer bit (TRANx bit) is set.
The TRAN1 bit controls the PWMx outputs driven
by counter 1 and the TRAN2 bit controls the
PWMx outputs driven by counter 2.
PWM generation and output compare are done by
comparing these active DCRx values with the
counter.
The maximum available resolution for the PWMx
duty cycle is:
Resolution = 1 / (4096 - ATR)
where ATR is equal to 0. With this maximum reso-
lution, 0% and 100% duty cycle can be obtained
by changing the polarity.
At reset, the counter starts counting from 0.
When a upcounter overflow occurs (OVF event),
the preloaded Duty cycle values are transferred to
the active Duty Cycle registers and the PWMx sig-
nals are set to a high level. When the upcounter
matches the active DCRx value the PWMx signals
are set to a low level. To obtain a signal on a
PWMx pin, the contents of the corresponding ac-
tive DCRx register must be greater than the con-
tents of the ATR register.
The maximum value of ATR is 4094 because it
must be lower than the DCR value which must be
4095 in this case.
Polarity Inversion
The polarity bits can be used to invert any of the
four output signals. The inversion is synchronized
with the counter overflow if the corresponding
transfer bit in the ATCSR2 register is set (reset
value). See Figure 3.
Figure 37. PWM Polarity Inversion
The Data Flip Flop (DFF) applies the polarity inver-
sion when triggered by the counter overflow input.
Output Control
The PWMx output signals can be enabled or disa-
bled using the OEx bits in the PWMCR register.
PWMx
PIN
counter
overflow
OPx
PWMxCSR Register
inverter
DFF
TRANx
ATCSR2 Register
1
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