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参数资料
| 型号： | ST7PLITE15BF0B3 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP20 |
| 封装： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-20 |
| 文件页数： | 158/159页 |
| 文件大小： | 2855K |
| 代理商： | ST7PLITE15BF0B3 |
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ST7LITE1xB
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10-BIT A/D CONVERTER (ADC) (Cont’d)
11.5.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by hard-
ware when software reads the ADCDRH register
or writes to any bit of the ADCCSR register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit de-
scription (ADCDRL register).
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: A/D converter and amplifier are switched off
1: A/D converter and amplifier are switched on
Bits 4:3 = Reserved. Must be kept cleared.
Bits 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent. Refer to
the device pinout description.
DATA REGISTER HIGH (ADCDRH)
Read Only
Reset Value: xxxx xxxx (xxh)
Bits 7:0 = D[9:2] MSB of Analog Converted Value
AMP CONTROL/DATA REGISTER LOW (AD-
CDRL)
Read/Write
Reset Value: 0000 00xx (0xh)
Bits 7:5 = Reserved. Forced by hardware to 0.
Bit 4 = AMPCAL Amplifier Calibration Bit
This bit is set and cleared by software. It is advised
to use this bit to calibrate the ADC when amplifier
is ON. Setting this bit internally connects amplifier
input to 0V. Hence, corresponding ADC output can
be used in software to eliminate amplifier-offset er-
ror.
0: Calibration off
1: Calibration on. (The input voltage of the amplifi-
er is set to 0V)
Bit 3 = SLOW Slow mode
This bit is set and cleared by software. It is used
together with the SPEED bit in the ADCCSR regis-
ter to configure the ADC clock speed as shown on
the table below.
70
EOC
SPEED ADON
0
CH2
CH1
CH0
Channel Pin*
CH2
CH1
CH0
AIN0
000
AIN1
001
AIN2
010
AIN3
011
AIN4
100
AIN5
101
AIN6
110
70
D9
D8
D7
D6
D5
D4
D3
D2
70
00
0
AMP
CAL
SLOW
AMP-
SEL
D1
D0
fADC
SLOW SPEED
fCPU/2
00
fCPU
01
fCPU/4
1x
1
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