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参数资料
| 型号： | ST7PLITE15BF0B3 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDIP20 |
| 封装： | 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-20 |
| 文件页数： | 132/159页 |
| 文件大小： | 2855K |
| 代理商： | ST7PLITE15BF0B3 |
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ST7LITE1xB
74/159
DUAL 12-BIT AUTORELOAD TIMER 4 (Cont’d)
BREAK CONTROL REGISTER (BREAKCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = BRSEL Break Input Selection
This bit is read/write by software and cleared by
hardware after reset. It selects the active Break
signal from external BREAK pin and the output of
the comparator.
0: External BREAK pin is selected for break mode.
1: Comparator output is selected for break mode.
Bit 6 = BREDGE Break Input Edge Selection
This bit is read/write by software and cleared by
hardware after reset. It selects the active level of
Break signal.
0: Low level of Break selected as active level.
1: High level of Break selected as active level.
Bit 5 = BA Break Active.
This bit is read/write by software, cleared by hard-
ware after reset and set by hardware when the ac-
tive level defined by the BREDGE bit is applied on
the BREAK pin. It activates/deactivates the Break
function.
0: Break not active
1: Break active
Bit 4 = BPEN Break Pin Enable.
This bit is read/write by software and cleared by
hardware after Reset.
0: Break pin disabled
1: Break pin enabled
Bits 3:0 = PWM[3:0] Break Pattern.
These bits are read/write by software and cleared
by hardware after a reset. They are used to force
the four PWMx output signals into a stable state
when the Break function is active and correspond-
ing OEx bit is set.
PWMx DUTY CYCLE REGISTER HIGH (DCRxH)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved.
PWMx DUTY CYCLE REGISTER LOW (DCRxL)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 11:0 = DCRx[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. It defines
the duty cycle of the corresponding PWM output
signal (see Figure 4).
In PWM mode (OEx=1 in the PWMCR register)
the DCR[11:0] bits define the duty cycle of the
PWMx output signal (see Figure 4). In Output
Compare mode, they define the value to be com-
pared with the 12-bit upcounter value.
INPUT CAPTURE REGISTER HIGH (ATICRH)
Read only
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved.
INPUT CAPTURE REGISTER LOW (ATICRL)
Read only
Reset Value: 0000 0000 (00h)
70
BRSEL BREDGE
BA
BPEN
PWM3
PWM2
PWM1 PWM0
15
8
0
DCR11 DCR10 DCR9
DCR8
70
DCR7
DCR6
DCR5
DCR4
DCR3
DCR2
DCR1
DCR0
15
8
0
ICR11 ICR10
ICR9
ICR8
70
ICR7
ICR6
ICR5
ICR4
ICR3
ICR2
ICR1
ICR0
1
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