参数资料
型号: ST7PLUSA2M6TR
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8
封装: 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8
文件页数: 136/136页
文件大小: 1705K
代理商: ST7PLUSA2M6TR
Obsolete
- Obsolete
Product(s)
Obsolete
- Obsolete
Product(s)
ST7LITEUS2, ST7LITEUS5
Electrical characteristics
12.4
Supply current characteristics
The following current consumption specified for the ST7 functional operating modes over
temperature range does not take into account the clock source current consumption. To get
the total device consumption, the two current values must be added (except for Halt mode
for which the clock is stopped). Refer to Section 12.4.2: Internal RC oscillator supply current
TA = -40 to +125 °C unless otherwise specified.
12.4.1
Supply current
Table 52.
Supply current characteristics
Symbol
Parameter
Conditions
Typ
Max
Unit
IDD
Supply current in Run mode (1)
V
DD
=5
V
fCPU = 4 MHz
2.5
4.5(2)
mA
fCPU = 8 MHz
5.0
7.5
Supply current in Wait mode(3)
fCPU = 4 MHz
0.85
2.0(2)
fCPU = 8 MHz
1.2
3.5
Supply current in Wait mode(4)
fCPU/32 = 250 kHz
600
950
μA
Supply current in Slow-Wait mode(5)
fCPU/32 = 250 kHz
450
750
Supply current in AWUFH mode (6)(7)
45
100(2)
Supply current in Active-halt mode
100
250
Supply current in Halt mode (8)
TA = 85 °C
0.5
3.0
TA = 125 °C
0.5
5.0
Supply current in Run mode(1)
V
DD
=3
V
fCPU = 4 MHz
1.30
2.0 (2)
mA
Supply current in Wait mode(3)
fCPU = 4 MHz
0.36
0.5 (2)
Supply current in Slow mode(4)
fCPU/32 = 250 kHz
300
400(2)
μA
Supply current in Slow-wait mode (5)
fCPU/32 = 250 kHz
250
350(2)
Supply current in AWUFH mode(6)(7)
20
50 (2)
Supply current in Active-halt mode
90
150(2)
Supply current in Halt mode(8)
TA = 85 °C
0.25
2.5 (2)
TA = 125 °C
0.25
4.5 (2)
1.
CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in
reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
2.
Data based on characterization, not tested in production.
3.
All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)
driven by external square wave, LVD disabled.
4.
All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (CLKIN)
driven by external square wave, LVD disabled.
5.
Slow-Wait mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or
VSS (no load), all peripherals in reset state; clock input (CLKIN) driven by external square wave, LVD disabled.
6.
All I/O pins in input mode with a static value at VDD or VSS (no load). Data tested in production at VDD max. and fCPU max.
7.
This consumption refers to the Halt period only and not the associated run period which is software dependent.
8.
All I/O pins in output mode with a static value at VSS (no load), LVD disabled. Data based on characterization results,
tested in production at VDD max and fCPU max.
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