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ST90158 - ELECTRICAL CHARACTERISTICS
EXTERNAL BUS TIMING TABLE
(VDD =5V ± 10%, TA = -40°C+ 85°C, Cload = 50pF, INTCLK = 16MHz, unless otherwise specified)
Note: The value in the left hand column shows the formula used to calculate the timing minimum or maximum from the oscillator clock period,
prescale value and number of wait cycles inserted.
The values in the right hand two columns show the timing minimum and maximum for an external clock at 24 MHz divided by 2, prescaler
value of zero and zero wait status.
Legend:
Tck = INTCLK period = OSCIN period when OSCIN is not divided by 2;
2*OSCIN period when OSCIN is divided by 2;
OSCIN period / PLL factor when the PLL is enabled
TckH = INTCLK high pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN high pulse width)
TckL = INTCLK low pulse width (normally = Tck/2, except when INTCLK = OSCIN, in which case it is OSCIN low pulse width)
P = clock prescaling value (=PRS; division factor = 1+P)
Wa = wait cycles on AS; = max (P, programmed wait cycles in EMR2, requested wait cycles with WAIT)
Wd = wait cycles on DS; = max (P, programmed wait cycles in WCR, requested wait cycles with WAIT)
N
°
Symbol
Parameter
Value (Note)
Unit
Formula
Min. Max.
1
TsA (AS)
Address Set-up Time before AS
↑
Tck*Wa+TckH-9
23
ns
2
ThAS (A)
Address Hold Time after AS
↑
TckL-4
28
ns
3
TdAS (DR)
AS
↑ to Data Available (read)
Tck*(Wd+1)+3
65
ns
4
TwAS
AS Low Pulse Width
Tck*Wa+TckH-5
27
ns
5
TdAz (DS)
Address Float to DS
↓
00
ns
6
TwDS
DS Low Pulse Width
Tck*Wd+TckH-5
27
ns
7
TdDSR (DR)
DS
↓ to Data Valid Delay (read)
Tck*Wd+TckH+4
35
ns
8
ThDR (DS)
Data to DS
↑ Hold Time (read)
7
ns
9
TdDS (A)
DS
↑ to Address Active Delay
TckL+11
43
ns
10
TdDS (AS)
DS
↑ to AS ↓ Delay
TckL-4
28
ns
11
TsR/W (AS)
R/W Set-up Time before AS
↑
Tck*Wa+TckH-17
15
ns
12
TdDSR (R/W)
DS
↑ to R/W and Address Not Valid Delay
TckL-1
31
ns
13
TdDW (DSW)
Write Data Valid to DS
↓ Delay
-16
ns
14
TsD(DSW)
Write Data Set-up before DS
↑
Tck*Wd+TckH-16
16
ns
15
ThDS (DW)
Data Hold Time after DS
↑ (write)
TckL-3
29
ns
16
TdA (DR)
Address Valid to Data Valid Delay (read)
Tck*(Wa+Wd+1)+TckH-7
86
ns
17
TdAs (DS)
AS
↑ to DS ↓ Delay
TckL-6
26
ns
1