参数资料
型号: STD12N05L
厂商: 意法半导体
英文描述: N-Channel Enhancement Mode Low Threshold Power MOS Transistor(N沟道增强模式低阈值功率MOSFET)
中文描述: N沟道增强模式的低阈值功率MOS晶体管(不适用沟道增强模式低阈值功率MOSFET的)
文件页数: 1/10页
文件大小: 175K
代理商: STD12N05L
STD12N05L
STD12N06L
N - CHANNEL ENHANCEMENT MODE
LOW THRESHOLD POWER MOS TRANSISTOR
I
TYPICAL R
DS(on)
= 0.115
I
AVALANCHE RUGGED TECHNOLOGY
I
100% AVALANCHE TESTED
I
REPETITIVE AVALANCHE DATA AT 100
o
C
I
LOW GATE CHARGE
I
LOGIC LEVEL COMPATIBLE INPUT
I
175
o
C OPERATING TEMPERATURE
I
APPLICATION ORIENTED
CHARACTERIZATION
I
THROUGH-HOLE IPAK (TO-251) POWER
PACKAGE IN TUBE (SUFFIX ”-1”)
I
SURFACE-MOUNTING DPAK (TO-252)
POWER PACKAGE IN TAPE & REEL
(SUFFIX ”T4”)
APPLICATIONS
I
HIGH CURRENT, HIGH SPEED SWITCHING
I
SOLENOID AND RELAY DRIVERS
I
REGULATORS
I
DC-DC & DC-AC CONVERTERS
I
MOTOR CONTROL, AUDIO AMPLIFIERS
I
AUTOMOTIVE ENVIRONMENT (INJECTION,
ABS, AIR-BAG, LAMPDRIVERS, Etc.)
INTERNAL SCHEMATIC DIAGRAM
TYPE
V
DSS
R
DS(on)
< 0.15
< 0.15
I
D
STD12N05L
50 V
12 A
STD12N06L
60 V
12 A
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
STD12N05L
STD12N06L
V
DS
Drain-source Voltage (V
GS
= 0)
Drain- gate Voltage (R
GS
= 20 k
)
Gate-source Voltage
Drain Current (continuous) at T
c
= 25
o
C
Drain Current (continuous) at T
c
= 100
o
C
50
60
V
V
DGR
50
60
V
V
GS
±
15
12
V
I
D
A
I
D
8
A
I
DM
(
)
P
tot
Drain Current (pulsed)
Total Dissipation at T
c
= 25
o
C
48
A
45
W
Derating Factor
0.3
W/
o
C
o
C
o
C
T
stg
Storage Temperature
-65 to 175
T
j
Max. Operating Junction Temperature
(
) Pulsewidth limited by safe operating area
175
November 1996
1
3
2
IPAK
TO-251
(Suffix ”-1”)
1
3
DPAK
TO-252
(Suffix ”T4”)
1/10
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