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参数资料
| 型号： | STEL-1175+125/MC |
| 厂商： | INTEL CORP |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, CQCC68 |
| 封装： | CERAMIC, LDCC-68 |
| 文件页数： | 14/14页 |
| 文件大小： | 253K |
| 代理商： | STEL-1175+125/MC |
9
STEL-1175+125
NCO PHASE CHANGE SEQUENCE
1. PHSEL=0. DIRECT LOADING.
ADDR 3-0
DATA
7-0
OUT 11-0
PHLD
PSYNC
CLOCK
DON'T CARE
12 CLOCK EDGES
OLD PHASE
NEW PHASE
DON'T CARE
t SU
t HD
t SU
t W
ELECTRICAL CHARACTERISTICS
A.C. CHARACTERISTICS (Operating Conditions: VDD= 5.0 V ±5%, VSS = 0 V, Ta= 0° to 70° C, Commercial
VDD= 5.0 V ±10%, VSS = 0 V, Ta = 55° to 125° C, Military)
tRS
RESET pulse width
tSR
RESET to CLOCK Setup
tSU
DATA, ADDR or CSEL
to WRSTB or PHLD Setup,
and FRLD or PHLD to
CLOCK Setup
tHD
DATA, ADDR or CSEL
to WRSTB or PHLD Hold,
and DATA and ADDR
to CLOCK Hold
tCH
CLOCK high
tCL
CLOCK low
tW
WRSTB, FRLD or PHLD
pulse width
tCD
CLOCK to output delay
3
nsec.
3
4
nsec.
fCLK = 125 MHz
3
4
nsec.
fCLK = 125 MHz
3
5
nsec.
3626
nsec.
Load = 15 pF
STEL-1175+125
(Commercial)
(Military)
Symbol
Parameter
Min. Max. Min. Max. Units
Conditions
3
nsec.
2
3
nsec.
10
25
nsec.
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