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参数资料
| 型号： | STEL-1175+125/MC |
| 厂商： | INTEL CORP |
| 元件分类： | 数字信号处理外设 |
| 英文描述： | 8-BIT, DSP-NUM CONTROLLED OSCILLATOR, CQCC68 |
| 封装： | CERAMIC, LDCC-68 |
| 文件页数： | 9/14页 |
| 文件大小： | 253K |
| 代理商： | STEL-1175+125/MC |
STEL-1175+125
4
MUX BLOCK
This block is used to select which -Phase Buffer Register
is used as the source of frequency data for the -Phase
Register, by means of the FRSEL input.
-PHASE REGISTER BLOCK
This block controls the updating of the -Phase word used
in the Accumulator. The frequency data from the Mux
Block is loaded into this block after a falling edge on the
FRLD input. This block also generates the FSYNC
output, which indicates the instant at which any frequency
change made at the inputs affects the OUT11-0 signals.
PHASE ACCUMULATOR BLOCK
This block forms the core of the NCO function. It is a
high-speed, pipelined, 32-bit parallel accumulator,
generating a new sum in every clock cycle. A carry input
(the CIN input) allows the resolution of the accumulator
to be expanded by means of an auxiliary NCO or phase
accumulator. The overflow signal is discarded (and is
available at the COUT pin), since the required output is
the modulo(232) sum only. This represents the modulo(2)
phase angle.
PHASE ALU BLOCK
The Phase ALU performs the addition of the PM data to
the Phase Accumulator output. The PM data word is 12
bits wide, and this is added to the 13 most significant bits
from the Phase Accumulator to form the modulated phase
used to address the lookup table. This block also generates
the PSYNC output, which indicates the instant at which
any phase change made at the inputs affects the OUT11-0
signals.
SINE/COSINE LOOKUP TABLE BLOCK
This block is the sine/cosine memory. The 13 bits from
the Phase ALU are used to address this memory to
generate the 12-bit OUT11-0 outputs. The output will be a
sine signal when the SINE input is high, and will be a
cosine signal when this input is low.
PHASE OUTPUT REGISTER BLOCK
The twelve most significant bits from the Phase ALU
Block are latched into the Phase Output Register on the
rising edges of the PHCLK input. The output of this
register is available on the PHASE11-0 pins.
INPUT SIGNALS
RESET
The RESET input is asynchronous and active low, and
clears all the registers in the device. When RESET goes
low, all registers are cleared within 20 nsecs, and normal
operation will resume after this signal returns high. The
data on the OUT11-0 bus will then be invalid for 6 rising
frequency. This ratio squared times the phase noise power
of the clock specified in a given bandwidth is the phase
noise power that may be expected in that same bandwidth
relative to the output frequency.
The NCO achieves its high operating frequency by making
extensive use of pipelining in its architecture. The pipeline
delays within the NCO represent 19 clock cycles. The dual
-Phase registers used in the STEL-1175 allow the
frequency to be updated as rapidly as every fourth clock
cycle, i.e. at 25% of the clock frequency. The pipeline delay
associated with the phase modulator is only 12 clock cycles,
since the phase modulating function is at the output of the
accumulator. The phase modulation may also be changed
as rapidly as every fourth clock cycle, at 25% of the clock
frequency, resulting in a maximum modulation rate of 30
MHz with a clock frequency of 125 MHz. Note that when
a phase or frequency change occurs at the output the
change is instantaneous, i.e., it occurs in one clock cycle,
with complete phase coherence.
FUNCTION BLOCK DESCRIPTION
ADDRESS SELECT LOGIC BLOCK
This block controls the writing of data into the device via
the DATA7-0 inputs. The data is written into the device on
the rising edge of the WRSTB input, and the register into
which the data is written is selected by the ADDR3-0 inputs.
The CSEL input can be used to selectively enable the
writing of data from the bus.
PHASE MODULATION CONTROL BLOCK
This block includes the Phase Modulation Buffer Register
and controls the source of the phase modulation (PM) data
by means of the PHSEL input. When this signal is low,
data from the DATA7-0 and ADDR3-0 inputs is written
directly into the Phase ALU after a falling edge on the
PHLD input. When PHSEL is high, data is written into
the Phase Modulation Buffer Register from the DATA7-0
bus on the rising edge of the WRSTB input. The data will
then be transferred into the Phase ALU after the next
falling edge of PHLD. The source of the PM data applied
to the Phase ALU will be the Phase Buffer Register in this
mode.
-PHASE BUFFER REGISTERS A & B BLOCK
The two -Phase Buffer Registers are used to temporarily
store the -Phase data written into the device. This allows
the data to be written asynchronously as four bytes per 32-
bit -Phase word. The data is transferred from these
registers into the -Phase Register after a falling edge on
the FRLD input.
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