- 您现在的位置：买卖IC网 > PDF目录98147 > STEL-1376 (INTEL CORP) SPECIALTY MICROPROCESSOR CIRCUIT, DIP65 PDF资料下载
参数资料
| 型号： | STEL-1376 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, DIP65 |
| 封装： | 3.350 X 1.500 INCH, 0.350 INCH HEIGHT, DIP-65 |
| 文件页数： | 10/13页 |
| 文件大小： | 233K |
| 代理商： | STEL-1376 |
STEL-1376
6
Since the propagation delay of this output from the
rising edges of the CLOCK input is comparable to the
clock period at 80 MHz, care should be taken when
using this output to synchronize the phase and
frequency changes. If this signal is not used, there is a
50% probability that the phase and frequency changes
will occur one cycle of the CLOCK input later than
specified.
POWER SUPPLY CONNECTIONS
It is recommended that adequate decoupling of the +5
volt and –5.2 volt power supplies be provided. In
addition, it is recommended that decoupling
inductors be used on the DVEE (DAC) and AVEE (DAC)
supplies to minimize the noise on the power supplies
to the DAC. Suitable values for the inductors are 0.3 to
1
H.
REFCLK
The Reference Clock output signal is the CLOCK
input divided by either eight or sixteen, depending on
the state of the CLKSEL input. When the input clock
frequency is set to 80 MHz to obtain precise 0.1 Hz
resolution, the frequency of the REFCLK signal will
then be either 10 or 5 MHz. It can be used in
conjunction with a phase locked loop (PLL) to lock the
80 MHz clock generator to a reference standard
frequency at one of these two frequencies.
LDCLK
The Load Clock output signal is the CLOCK input
divided by two. This clock is used for loading the
phase and frequency data from the buffer registers to
the Phase ALU and
-Phase Register, respectively.
This output can be used to determine the exact clock
cycle during which these transfers will take place, as
shown in the timing diagrams. The transfers will take
place on the rising edge of the CLK following the
falling edge of FRLD or PHLD when LDCLK is low.
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Warning: Stresses greater than those shown below may cause permanent damage
to the device. Exposure of the device to these conditions for extended periods
may also affect device reliability.
Symbol
Parameter
Range
Units
Tstg
Storage Temperature
–65 to +125
°C
Ta
Operating Temperature
–40 to +85
°C
VDDmax
Max. voltage between VDD and VSS
+7 to –0.7
volts
VEEmax
Max. voltage between VEE and VSS
–7 to +0.7
volts
VI/O(max)
Max. voltage on any input pin
VDD + 0.7
volts
VI/O(min)
Min. voltage on any input pin
VSS – 0.7
volts
RECOMMENDED OPERATING CONDITIONS
(The VSS pins should be connected to ground)
Symbol
Parameter
Range
Units
VDD
Supply Voltage, +5 volts
+5
± 10%
volts
VEE
Supply Voltage, –5.2 volts
–5.2
± 10%
volts
Ta
Operating Temperature (Ambient)
0 to +50
°C (70°C case)
相关PDF资料 |
PDF描述 |
|---|---|
| STEL-1377Q | SPECIALTY MICROPROCESSOR CIRCUIT, DIP63 |
| STK1390-5S25I | 0 TIMER(S), REAL TIME CLOCK, PDSO32 |
| STK1390-5S30I | 0 TIMER(S), REAL TIME CLOCK, PDSO32 |
| STK1390-5S35 | 0 TIMER(S), REAL TIME CLOCK, PDSO32 |
| STK1390-5W30I | 0 TIMER(S), REAL TIME CLOCK, PDIP32 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| STEL-1377Q | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FREQUENCY SYNTHESIZER|DIP|64PIN|PLASTIC |
| STEL-1377S | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FREQUENCY SYNTHESIZER|DIP|64PIN|PLASTIC |
| STEL-1378A | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FREQUENCY SYNTHESIZER|HYBRID|DIP|64PIN|PLASTIC |
| STEL-2000A+20/CR | 制造商:未知厂家 制造商全称:未知厂家 功能描述:RF MODULATOR/DEMODULATOR|CMOS|QFP|100PIN|PLASTIC |
| STEL-2000A+45/CR | 制造商:未知厂家 制造商全称:未知厂家 功能描述:RF MODULATOR/DEMODULATOR|CMOS|QFP|100PIN|PLASTIC |
发布紧急采购，3分钟左右您将得到回复。