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参数资料
| 型号： | STEL-1376 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, DIP65 |
| 封装： | 3.350 X 1.500 INCH, 0.350 INCH HEIGHT, DIP-65 |
| 文件页数： | 2/13页 |
| 文件大小： | 233K |
| 代理商： | STEL-1376 |
STEL-1376
10
APPLICATIONS INFORMATION
Since the STEL-1376 combines high-speed digital and
analog circuits, care must be taken to minimize the
effects of noise from the digital circuit on the analog
output. The following precautions will help in this
area:
1.
Use ground and power planes on the printed
circuit board. Separate analog and digital ground
planes will also help.
2.
Decouple the analog VEE line from the VEE supply
with a 1
H inductor.
3.
Decouple all the power supply pins and the VREF
pin to the appropriate ground plane with 1000 pF
and 0.1
F ceramic capacitors mounted as closely
as possible to the pins.
The clock input can be either a sine wave or a square
wave, the input buffer will square up a sinusoidal
input. The input is capacitively coupled internally. An
ECL level signal or a sine wave at about –5 to +5 dBm
(50
) is recommended.
Recommended bias circuit for VREF
Ana. GND
–5.2 V (Ana.)
2.7 K
2.2 K
2 K
VREF
V
65
62
61
STEL-1376
SS
EE
AV
2.5 V
DATA BUS CONNECTIONS FOR DATA
LOADING IN THE BYTE-WIDE MODE
When the addresses are set for byte wide
operation the DATA34-0 bus must be
connected as shown in the diagram for correct
operation.
D0
D1
D2
D3
D4
D5
D6
D7
STEL-1376
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
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相关代理商/技术参数 |
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