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参数资料
| 型号： | STEL-1376 |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, DIP65 |
| 封装： | 3.350 X 1.500 INCH, 0.350 INCH HEIGHT, DIP-65 |
| 文件页数： | 8/13页 |
| 文件大小： | 233K |
| 代理商： | STEL-1376 |
STEL-1376
4
CIRCUIT DESCRIPTION
The frequency of the NCO is determined by the
number stored in the
-Phase register which is
programmed from the interface bus. The number
stored in the
-Phase register is added to the current
contents of the accumulator every clock cycle to
generate a monotonically increasing phase angle. The
NCO generates digitized sine functions by addressing
a sine lookup table with the phase accumulator. Phase
modulation data is added to the accumulator output
before the lookup table. In the STEL-1176 NCO the
accumulator has an 83/4 decade 1-2-4-8 BCD
architecture, allowing it generate frequencies which
have a decimal relationship to the clock frequency.
The NCO is controlled either from a microprocessor
based or parallel interface. Data can be written into the
frequency control registers from the data bus either as
five bytes or as a single 35-bit word. The phase
modulation data is loaded as a 3-bit word on the
separate bus. Please refer to the STEL-1176 data sheet
for information on programming the NCO.
The NCO output is passed through CMOS to ECL level
translators and loaded synchronously into a high-
speed 10-bit DAC. The full-scale output of the DAC is
determined by the voltage on the VREF input, and this
can be used to amplitude modulate the output signal.
FUNCTION BLOCK DESCRIPTION
NCO BLOCK
The NCO block is the core of the STEL-1376 DDS. It
consists of a front-end which may be programmed
from the control inputs. The NCO is described fully in
the STEL-1176 data sheet. Please refer to this data sheet
for more detailed information.
LEVEL TRANSLATOR BLOCK
The outputs of the NCO block are CMOS level digital
signals. These are translated to ECL levels for
optimum operation of the DAC.
CLOCK GENERATION BLOCK
The clock generation block generates the different
clocks required for the NCO and DAC blocks from the
incoming ECL or sinusoidal clock signal.
DAC BLOCK
The DAC block consists of the Sony CX20201A-1
digital to analog converter and the necessary
supporting circuitry.
INPUT SIGNALS
RESET
The RESET input is asynchronous and active low, and
clears all the registers in the device. When RESET goes
low, all registers are cleared within 13 nsecs, and
normal operation will resume after this signal returns
high. The data on the OUT11-0 bus will then be invalid
for 10 clock cycles, and thereafter will remain at the
value corresponding to zero phase (801H) until new
frequency or phase data is loaded with the FRLD or
PHLD
inputs after the RESET returns high.
CLOCK
All synchronous functions performed within the NCO
are referenced to the rising edge of the CLOCK input.
The CLOCK signal should nominally be a square
wave at a maximum frequency of 80 MHz. A non-
repetitive CLOCK waveform is permissible as long as
the minimum duration positive or negative pulse on
the waveform is always greater than 5 nanoseconds.
CSEL
The Chip Select input is used to control the writing of
data into the chip. It is active low. When this input is
high all data writing via the DATA7-0 bus is inhibited.
DATA34 through DATA0
The 35-bit DATA34-0 bus is used to program the 35-bit
-Phase Register. DATA
0 is the least significant bit of
the bus. The data programmed into the
-Phase
register in this way determines the output frequency
of the NCO. The data will be loaded as a parallel 35-bit
word or as five bytes, depending on the state of the
address bus, as shown in the address table. Each nibble
(4 bits) of data starting at DATA3-0 represents one
decade of frequency data in 1-2-4-8 BCD format. When
the byte-wide mode is selected (addresses 000 to 100),
the 35 data lines must be connected externally to form
an 8-bit data bus as follows:
Connect DATA34-32 to DATA2-0,
DATA31-24 to DATA23-16 to DATA15-8 to DATA7-0.
PHASE2 through PHASE0
The 3-bit PHASE2-0 bus is used to program the 3-bit
Phase Register. PHASE0 is the least significant bit of
the bus. PHASE2 corresponds to an incremental phase
shift of 180
°, PHASE
1 corresponds to an incremental
phase shift of 90
°, and PHASE
0 corresponds to an
incremental phase shift of 45
°.
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