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参数资料
| 型号： | STEL-1378A |
| 英文描述： | FREQUENCY SYNTHESIZER|HYBRID|DIP|64PIN|PLASTIC |
| 中文描述： | 频率合成器|混合|双酯| 64管脚|塑料 |
| 文件页数： | 6/19页 |
| 文件大小： | 284K |
| 代理商： | STEL-1378A |
STEL-2060C
6
ADDR
2-0
The 3-bit address bus is used to access the various I/O
functions, as shown in the Memory Map table, below. Note
that some addresses contain both Read and Write registers.
These read and write mode registers are separate and contain
different data.
WRITE
The
Write
input is used to write data to the microprocessor
data bus. It is active low and is normally connected to the
write line of the host processor.
READ
The
Read
input is used to read data from the microprocessor
data bus. It is active low and is normally connected to the
read line of the host processor.
CSEL
The
C
hip
Sel
ect input can be used to selectively enable the
microprocessor data bus. It is active low.
INT
The
Int
errupt output indicates when the Period Counter in
the BER Monitor has completed a count period, and that a
new value of
BERCT
is ready to be read from addresses 0
H
and 1
H
, when
INT
will go high for one symbol period.
INPUT (WRITE) FUNCTIONS
COUNT
7-0
The 8-bit
COUNT
7-0
data defines the period (i.e., the number
of bits) used in the node synchronization circuit. The 8-bit
number N is used to set up a period of (256N + 256) internally,
where N is the value of
COUNT
7-0
. If the renormalization
count exceeds the threshold value during a period of this
number of bits then an out-of-sync condition is declared (i.e.,
the output pin
OOS
is set high and
AUTO
pulses high).
Reset value 00
H
.
THR
7-0
The 8-bit
THR
7-0
data defines the threshold for node
synchronization when
EXTSEL
is set low. The function is
identical to that of the
THR
7-0
input signal. Reset value 00
H
.
BPER
23-0
The 24-bit
B
ER
Per
iod data is used to set the period (number
of data bits) over which the mean BER is measured by the
BER Monitor. The period used is 1000 times the value of
BPER
23-0
. Reset value FFFFFF
H
.
Note:
The BER Count function incorporated in the
STEL-2060CCC uses a counter to count the number of
thousands of bits received. When the value of this counter is
equal
to the value written into BPER
23-0
the number of errors
counted is dumped into the BERCT
15-0
output register and
can be read from read addresses 0-1
H
. Simultaneously, both
the error and bit counters are reset and the process is restarted,
and an interrupt (INT) is generated to indicate that the new
value is ready to be read.
Since the default (reset) value of the BPER
23-0
register is
FF FF FF
H
a potential problem occurs if the desired value is
not written into this register before the value of the counter
has already incremented past this value. If this is not done
the equality will not be detected until after the counter
overflows and increments to the desired value once again.
Even at the maximum rate of 45 Mbps this will take over 6
minutes and, at a more modest data rate, such as 1 Mbps, it
will take over 4
1
/
2
hours! In any case, the user can easily be
misled into believing that the circuit is not operating correctly
since the interrupts will not be generated as expected. It is
therefore imperative that the BPER
23-0
value be written into
the STEL-2060CCC as soon as possible after a reset to ensure
that this condition does not take place. The maximum time
allowable is just less than the desired interrupt period itself,
since the counter begins counting right after the reset is
released.
e.g., if the desired interrupt period is one second, the
BPER
23-0
value must be written within one second of the
reset. At a data rate of 1 Mbps the period would correspond
to 10
6
bits and the correct BPER
23-0
value would be 10
3
, or
00 03 E8
H
.
If, for some reason, it is not possible to do this, a dummy
value should first be written into the STEL-2060CCC. This
should be large enough so that, at the time of writing, the bit
counter will not have exceeded the dummy value. In this
way the first interrupt will be generated within a reasonable
period of time and the dummy value can then be overwritten
with the desired value. Again, care must be taken to ensure
that the BPER
23-0
value written is greater than the
instantaneous counter value, otherwise the same problem
will occur.
e.g., in the above example, if it is not possible to write the
BPER
23-0
value until 5 seconds after the reset, then a dummy
BPER
23-0
value corresponding to >5 seconds, e.g., 6 seconds,
or 00 17 70
H
should first be written. The desired value of
00 03 E8
H
must then be written within one second of an
interrupt generated by the STEL-2060CCC, thereby ensuring
that the counter has not exceeded the new value at that time.
OUTPUT (READ) FUNCTIONS
BERCT
15-0
The 16-bit
B
it
Er
ror
C
oun
t
data represents the mean Bit Error
Rate over the period determined by the BER Period data
BPER
23-0
. The actual BER is given by:
8 x
BERCT
15-0
1000 x
BPER
23-0
BER =
The value will be updated each time the period counter
completes its count. Completion is indicated by the
INT
output going high for one clock cycle. If the accumulator
overflows during a measurement period its output will be
caused to saturate at a value of FFFF
H
.
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