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参数资料
| 型号： | STEL-1378A |
| 英文描述： | FREQUENCY SYNTHESIZER|HYBRID|DIP|64PIN|PLASTIC |
| 中文描述： | 频率合成器|混合|双酯| 64管脚|塑料 |
| 文件页数： | 9/19页 |
| 文件大小： | 284K |
| 代理商： | STEL-1378A |
9
STEL-2060C
the decoder will then continue to operate correctly provided
that nothing occurs to upset this cycle. This method exploits
the fact that not all falling edges of DCLKIN have a timing
sensitivity relative to the rising edges of SYMCKIN, as was
discussed earlier. For example, in rate
7
/
8
operation only
every fourth falling edge of DCLKIN is critical, starting with
the fourth one after the reset is released. By timing the rising
edge of the reset at a point in the cycle where there is good
separation between the rising edge of SYMCKIN and the
following falling edge of DCLKIN the same situation will
occur again every four cycles of DCLKIN, which is precisely
where the timing sensitivity occurs, as shown in the figure.
This method ensures good timing margins for stable operation
at all data rates up to 40 Mbps, this limit again being set by
the symbol setup and hold time requirements and need to
use square waves for the clocks.
ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Warning:
Stresses greater than those shown below may cause permanent damage to the
device. Exposure of the device to these conditions for extended periods may also affect device
reliability.
Symbol
Parameter
Range
Units
°
C
°
C
T
stg
T
a
V
DDmax
V
I/O(max)
V
I/O(min)
Storage Temperature
–65 to +150
Operating Temperature (Ambient)
–40 to +85
Max. voltage between V
DD
and V
SS
Max. voltage on any input or output pin
+7 to –0.7
volts
V
DD
+ 0.3
V
SS
– 0.3
volts
Min. voltage on any input or output pin
volts
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Range
+5
±
10%
Units
V
DD
T
a
Supply Voltage
volts
°
C
Operating Temperature (Ambient)
0 to +70
D.C. CHARACTERISTICS
(Operating Conditions: V
DD
= 5.0
±
5% volts, T
a
= 0
°
to 70
°
C)
Symbol
Parameter
Min. Typ.
Max.
Units
Conditions
I
DD(Q)
I
DD
V
IH(min)
V
IL(max)
V
OH(min)
V
OL(max)
I
IH(max)
I
IL(max)
Supply Current, Quiescent
1.0
mA
Static, no clock
Supply Current, Operational
8
mA/Mbps
@ 45 Mbps (
f
DATA
)
Guaranteed Logic '1'
Min. High Level Input Voltage
2.0
volts
Max. Low Level Input Voltage
0.8
volts
Guaranteed Logic '0'
Min. High Level Output Voltage
2.4
volts
I
O
= –4.0 mA
I
O
= +4.0 mA
V
IN
= +5.0 volts
V
IN
= 0 volts
Max. Low Level Output Voltage
0.4
volts
μ
A
μ
A
Max. High Level Input Current
10
Max. Low Level Input Current
–10
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