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参数资料
| 型号： | STK17TA8-W25 |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDIP40 |
| 封装： | 0.600 INCH, 0.100 INCH PITCH, PLASTIC, DIP-40 |
| 文件页数： | 5/25页 |
| 文件大小： | 285K |
| 代理商： | STK17TA8-W25 |
STK17TA8
April 2005
Document Control #ML0025 rev 1.1
13
HARDWARE STORE (HSB )
OPERATION
The STK17TA8 provides the HSB pin for controlling
and acknowledging the STORE operations. The HSB
pin can be used to request a hardware STORE cycle.
When the HSB pin is driven low, the STK17TA8 will
conditionally initiate a STORE operation after tDELAY.
An actual STORE cycle will only begin if a WRITE to
the SRAM took place since the last STORE or
RECALL
cycle. The HSB pin also acts as an open
drain driver that is internally driven low to indicate a
busy condition while the STORE (initiated by any
means) is in progress.
SRAM READ and WRITE operations that are in
progress when HSB is driven low by any means are
given time to complete before the STORE operation
is initiated. After HSB goes low, the STK17TA8 will
continue SRAM operations for tDELAY. During tDELAY,
multiple SRAM READ operations may take place. If
a WRITE is in progress when HSB is pulled low it
will be allowed a time, tDELAY, to complete. However,
any SRAM WRITE cycles requested after HSB goes
low will be inhibited until HSB returns high.
During any STORE operation, regardless of how it
was initiated, the STK17TA8 will continue to drive
the HSB pin low, releasing it only when the STORE
is complete. Upon completion of the STORE
operation the STK17TA8 will remain disabled until
the HSB pin returns high.
If HSB is not used, it should be left unconnected.
HARDWARE RECALL (POWER-UP)
During power up, or after any low-power condition
(VCC < VSWITCH), an internal RECALL request will be
latched. When VCC once again exceeds the sense
voltage
of
VSWITCH,
a
RECALL
cycle
will
automatically be initiated and will take tHRECALL to
complete.
SOFTWARE STORE
Data can be transferred from the SRAM to the
nonvolatile memory by a software address sequence.
The STK17TA8 software STORE cycle is initiated by
executing sequential E controlled READ cycles from
six specific address locations in exact order. During
the STORE cycle an erase of the previous nonvolatile
data is first performed, followed by a program of the
nonvolatile elements. Once a STORE cycle is
initiated, further input and output are disabled until the
cycle is completed.
Because a sequence of READs from specific
addresses is used for STORE initiation, it is important
that no other READ or WRITE accesses intervene in
the sequence, or the sequence will be aborted and no
STORE
or RECALL will take place.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1. Read address
0x4E38
Valid READ
2. Read address
0xB1C7
Valid READ
3. Read address
0x83E0
Valid READ
4. Read address
0x7C1F
Valid READ
5. Read address
0x703F
Valid READ
6. Read address
0x8FC0
Initiate STORE cycle
The software sequence may be clocked with E
controlled READs or G controlled READs.
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ cycles
and not WRITE cycles be used in the sequence,
although it is not necessary that G be low for the
sequence to be valid. After the tSTORE cycle time has
been fulfilled, the SRAM will again be activated for
READ and WRITE operation.
SOFTWARE RECALL
Data can be transferred from the nonvolatile memory
to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence of
READ operations in a manner similar to the software
STORE
initiation. To initiate the RECALL cycle, the
following sequence of E controlled READ operations
must be performed:
1. Read address
0x4E38
Valid READ
2. Read address
0xB1C7
Valid READ
3. Read address
0x83E0
Valid READ
4. Read address
0x7C1F
Valid READ
5. Read address
0x703F
Valid READ
6.
Read address
0x4C63
Initiate RECALL cycle
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