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参数资料
| 型号： | STK17TA8-W25 |
| 元件分类： | 时钟/数据恢复及定时提取 |
| 英文描述： | REAL TIME CLOCK, PDIP40 |
| 封装： | 0.600 INCH, 0.100 INCH PITCH, PLASTIC, DIP-40 |
| 文件页数： | 8/25页 |
| 文件大小： | 285K |
| 代理商： | STK17TA8-W25 |
STK17TA8
April 2005
Document Control #ML0025 rev 1.1
16
If a battery is used, a 3V lithium is recommended and
the STK17TA8 will only source current from the bat-
tery when the primary power is removed. The battery
will not, however, be recharged at any time by the
STK17TA8. The battery capacity should be chosen
for total anticipated cumulative down-time required
over the life of the system.
STOPPING AND STARTING THE OSCIL-
LATOR
The OSCEN bit in calibration register at 0x1FFF8
controls the starting and stopping of the oscillator.
This bit is nonvolatile and shipped to customers in the
"enabled" (set to 0) state. To preserve battery life
while system is in storage OSCEN should be set to a
1. This will turn off the oscillator circuit extending the
battery life. If the OSCEN bit goes from disabled to
enabled, it will take approximately 5 seconds (10
seconds max) for the oscillator to start.
The STK17TA8 has the ability to detect oscillator
failure.
This is recorded in the OSCF (Oscillator
Failed bit) of the flags register at address 0x1FFF0.
When the device is powered on (VCC goes above
Vswitch) the OSCEN bit is checked for "enabled" status.
If the OSCEN bit is enabled and the oscillator is not
active, the OSCF bit is set. The user should check for
this condition and then write a 0 to clear the flag. It
should be noted that in addition to setting the OSCF
flag bit, the time registers are reset to the “Base Time”
(see the section “Setting the Clock”), which is the
value last written to the timekeeping registers. The
Control/Calibration register and the OSCEN bit are not
affected by the oscillator failed condition.
If the voltage on the backup supply (either VRTCcap or
VRTCbat) falls below their respective minimum level the
oscillator may fail, leading to the oscillator failed
condition which can be detected when system power
is restored.
The value of OSCF should be reset to 0 when the
time registers are written for the first time. This will
initialize the state of this bit which may have become
set when the system was first powered on.
CALIBRATING THE CLOCK
The RTC is driven by a quartz controlled oscillator
with a nominal frequency of 32.768 KHz. Clock
accuracy will depend on the quality of the crystal,
usually specified to 35 ppm limits at 25
°C. This error
could equate to + 1.53 minutes per month. The
STK17TA8 employs a calibration circuit that can
improve the accuracy to +1/-2 ppm at 25
°C. The
calibration circuit adds or subtracts counts from the
oscillator divider circuit.
The number of times pulses are suppressed (sub-
tracted, negative calibration) or split (added, positive
calibration) depends upon the value loaded into the
five calibration bits found in calibration register at
0x1FFF8. Adding counts speeds the clock up;
subtracting counts slows the clock down. The
Calibration bits occupy the five lower order bits in the
control register 8. These bits can be set to represent
any value between 0 and 31 in binary form. Bit D5 is a
Sign bit, where a “1” indicates positive calibration and
a “0” indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the
cycle may, once per minute, have one second either
shortened by 128 or lengthened by 256 oscillator
cycles.
If a binary “1” is loaded into the register, only the first
2 minutes of the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so
on. Therefore each calibration step has the effect of
adding 512 or subtracting 256 oscillator cycles for
every 125,829,120 actual oscillator cycles. That is
+4.068 or -2.034 ppm of adjustment per calibration
step in the calibration register.
In order to determine how to set the calibration one
may set the CAL bit in the flags register at 0x1FFF0 to
1, which causes the INT pin to toggle at a nominal
512 Hz. Any deviation measured from the 512 Hz will
indicate the degree and direction of the required
correction. For example, a reading of 512.010124 Hz
would indicate a +20 ppm error, requiring a -10
(001010) to be loaded into the Calibration register.
Note that setting or changing the calibration register
does not affect the frequency test output frequency.
ALARM
The alarm function compares user-programmed val-
ues to the corresponding time-of-day values. When a
match occurs, the alarm event occurs. The alarm
drives an internal flag, AF, and may drive the INT pin
if desired.
There are four alarm match fields. They are date,
hours, minutes and seconds. Each of these fields also
has a Match bit that is used to determine if the field is
used in the alarm match logic. Setting the Match bit to
“0” indicates that the corresponding field will be used
in the match process.
Depending on the Match bits, the alarm can occur as
specifically as one particular second on one day of
the month, or as frequently as once per second
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