参数资料
型号: STK17TA8RF25I
元件分类: 时钟/数据恢复及定时提取
英文描述: REAL TIME CLOCK, PDSO48
封装: 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, PLASTIC, SSOP-48
文件页数: 4/27页
文件大小: 712K
代理商: STK17TA8RF25I
STK17TA8
July 2006
Document Control #ML0025 rev 1.4
12
nvSRAM
The STK17TA8 nvSRAM is made up of two
functional components paired in the same physical
cell. These are a SRAM memory cell and a
nonvolatile
QuantumTrap
cell
.
The
SRAM
memory cell operates as a standard fast static
RAM. Data in the SRAM can be transferred to the
nonvolatile cell (the STORE operation), or from
the nonvolatile cell
to SRAM (the RECALL
operation). This unique architecture allows all cells
to be stored and recalled in parallel. During the
STORE
and RECALL operations SRAM READ and
WRITE operations are inhibited. The STK17TA8
supports unlimited reads and writes just like a
typical SRAM. In addition, it provides unlimited
RECALL
operations from the nonvolatile cells and
up to 500K STORE operations.
SRAM READ
The STK17TA8 performs a READ cycle whenever
E
and G are low while W and HSB are high.
The address specified on pins A16-0 determines
which of the 131,056 data bytes will be accessed.
When the READ is initiated by an address
transition, the outputs will be valid after a delay of
tAVQV (READ cycle #1). If the READ is initiated by
E
or G , the outputs will be valid at tELQV or at
tGLQV, whichever is later (READ cycle #2). The data
outputs will repeatedly respond to address
changes within the tAVQV access time without the
need for transitions on any control input pins, and
will remain valid until another address change or
until E or G is brought high, or W or HSB is
brought low.
VCC
V
CA
P
10k
O
h
m
0.1
F
VCC
VCAP
W
SRAM WRITE
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-7 will be written into the memory if it is valid tDVWH
before the end of a W controlled WRITE or tDVEH
before the end of an E controlled WRITE.
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry will
turn off the output buffers tWLQZ after W goes low.
AutoStore OPERATION
The STK17TA8 stores data to nvSRAM using one of
three storage operations. These three operations are
Hardware Store, activated by HSB , Software Store,
actived by an address sequence, and AutoStore, on
device power down.
AutoStore
operation is a unique feature of Simtek
QuantumTrap
technology and is enabled by default
on the STK17TA8.
During normal operation, the device will draw current
from Vcc to charge a capacitor connected to the Vcap
pin. This stored charge will be used by the chip to
perform a single STORE operation. If the voltage on
the Vcc pin drops below Vswitch, the part will
automatically disconnect the Vcap pin from Vcc. A
STORE operation will be initiated with power provided
by the Vcap capacitor.
Figure 5 shows the proper connection of the storage
capacitor (Vcap) for automatic store operation. Refer to
the DC CHARACTERISTICS table for the size of Vcap.
The voltage on the Vcap pin is driven to 5V by a
charge pump internal to the chip. A pull up should be
placed on W to hold it inactive during power up.
To reduce unneeded nonvolatile stores, AutoStore
and Hardware Store operations will be ignored unless
at least one WRITE operation has taken place since
the most recent STORE or RECALL cycle. Software
initiated STORE cycles are performed regardless of
whether a WRITE operation has taken place. The
HSB
signal can be monitored by the system to detect
an AutoStore cycle is in progress.
DEVICE OPERATION
Figure 5: AutoStore
TM Mode
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