参数资料
型号: STK17TA8RF25I
元件分类: 时钟/数据恢复及定时提取
英文描述: REAL TIME CLOCK, PDSO48
封装: 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, PLASTIC, SSOP-48
文件页数: 6/27页
文件大小: 712K
代理商: STK17TA8RF25I
STK17TA8
July 2006
Document Control #ML0025 rev 1.4
14
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the
nonvolatile information is transferred into the SRAM
cells. After the tRECALL cycle time the SRAM will
once again be ready for READ and WRITE
operations. The RECALL operation in no way alters
the data in the nonvolatile elements.
DATA PROTECTION
The STK17TA8 protects data from corruption
during low-voltage conditions by inhibiting all
externally initiated STORE and WRITE operations.
The low-voltage condition is detected when VCC <
VSWITCH .
If the STK17TA8 is in a WRITE mode (both E and
W
low ) at power-up, after a RECALL, or after a
STORE, the WRITE will be inhibited until a
negative transition on E or W
is detected. This
protects against inadvertent writes during power up
or brown out conditions.
NOISE CONSIDERATIONS
The STK17TA8 is a high-speed memory and so must
have
a
high-frequency
bypass
capacitor
of
approximately 0.1
F connected between VCC and VSS,
using leads and traces that are as short as possible. As
with all high-speed CMOS ICs, careful routing of power,
ground and signals will reduce circuit noise.
LOW AVERAGE ACTIVE POWER
CMOS technology provides the STK17TA8 this the
benefit of drawing significantly less current when it is
cycled at times longer than 50ns. Figure 6 shows the
relationship between ICC and READ/WRITE cycle time.
Worst-case
current
consumption
is
shown
for
commercial temperature range, VCC = 3.6V, and chip
enable at maximum frequency. Only standby current is
drawn when the chip is disabled. The overall average
current drawn by the STK17TA8 depends on the
following items:
1. The duty cycle of chip enable.
2. The overall cycle rate for accesses.
3. The ratio of READs to WRITEs.
4. The operating temperature.
5. The VCC level.
6. I/O loading.
Ave
rage
A
cti
ve
C
urre
nt
(m
A)
100 150 200 300
0
10
20
30
40
50
Writes
Reads
Cycle Time (ns)
50
Figure 6 Current vs. Cycle time
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