参数资料
型号: STM32F103C6T7XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PQFP48
封装: 7 X 7 MM, ROHS COMPLIANT, LQFP-48
文件页数: 62/80页
文件大小: 1067K
代理商: STM32F103C6T7XXX
STM32F103x4, STM32F103x6
Electrical characteristics
Doc ID 15060 Rev 3
Figure 29.
ADC accuracy characteristics
Table 48.
ADC accuracy(1) (2) (3)
1.
ADC DC accuracy values are measured after internal calibration.
2.
Better performance could be achieved in restricted VDD, frequency and temperature ranges.
3.
ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-
robust) analog input pins should be avoided as this significantly reduces the accuracy of the conversion
being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to
standard analog pins which may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 5.3.12 does not
affect the ADC accuracy.
Symbol
Parameter
Test conditions
Typ
Max(4)
4.
Based on characterization, not tested in production.
Unit
ET
Total unadjusted error
fPCLK2 = 56 MHz,
fADC = 14 MHz, RAIN < 10 k,
VDDA = 2.4 V to 3.6 V
Measurements made after
ADC calibration
±2
±5
LSB
EO
Offset error
±1.5
±2.5
EG
Gain error
±1.5
±3
ED
Differential linearity error
±1
±2
EL
Integral linearity error
±1.5
±3
EO
EG
1LSBIDEAL
(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line
ET=Total Unadjusted Error: maximum deviation
between the actual and the ideal transfer curves.
EO=Offset Error: deviation between the first actual
transition and the first ideal one.
EG=Gain Error: deviation between the last ideal
transition and the last actual one.
ED=Differential Linearity Error: maximum deviation
between actual steps and the ideal one.
EL=Integral Linearity Error: maximum deviation
between any actual transition and the end point
correlation line.
4095
4094
4093
5
4
3
2
1
0
7
6
1
2
3
456
7
4093 4094 4095 4096
(1)
(2)
ET
ED
EL
(3)
VDDA
VSSA
ai14395b
VREF+
4096
(or
depending on package)]
VDDA
4096
[1LSBIDEAL =
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