参数资料
型号: STM32F103VEH6
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PBGA100
封装: 10 X 10 MM, 0.50 MM PITCH, ROHS COMPLIANT, LFBGA-100
文件页数: 101/115页
文件大小: 1225K
代理商: STM32F103VEH6
Electrical characteristics
STM32F103xC, STM32F103xD, STM32F103xE
I2S - SPI characteristics
Unless otherwise specified, the parameters given in Table 52 for SPI or in Table 53 for I2S
are derived from tests performed under ambient temperature, fPCLKx frequency and VDD
supply voltage conditions summarized in Table 10.
Refer to Section 5.3.13: I/O port characteristics for more details on the input/output alternate
function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S).
Table 52.
SPI characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fSCK
1/tc(SCK)
SPI clock frequency
Master mode
18
MHz
Slave mode
18
tr(SCK)
tf(SCK)
SPI clock rise and fall
time
Capacitive load: C = 30 pF
8
ns
tsu(NSS)
(2)
NSS setup time
Slave mode
4tPCLK
th(NSS)
NSS hold time
Slave mode
60
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode, fPCLK = 36 MHz, presc = 4
50
60
tsu(MI)
tsu(SI)
Data input setup time
Master mode - SPI1
3
Master mode - SPI2
5
Slave mode
4
th(MI)
Data input hold time
Master mode - SPI1
4
Master mode - SPI2
6
th(SI)
Slave mode
5
ta(SO)
(2)(3)
Data output access time
Slave mode, fPCLK = 36 MHz, presc = 4
0
55
Slave mode, fPCLK = 24 MHz
4tPCLK
tdis(SO)
Data output disable time Slave mode
10
tv(SO)
Data output valid time
Slave mode (after enable edge)
25
tv(MO)
Data output valid time
Master mode (after enable edge)
6
th(SO)
Data output hold time
Slave mode (after enable edge)
25
Master mode (after enable edge)
6
1.
Remapped SPI1 characteristics to be determined.
2.
Based on characterization, not tested in production.
3.
Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
4.
Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z
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