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参数资料
型号： STM32F105RBT7XXX
厂商： STMICROELECTRONICS
元件分类： 微控制器/微处理器
英文描述： 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PQFP64
封装： 10 X 10 MM, ROHS COMPLIANT, LQFP-64
文件页数： 65/95页
文件大小： 1007K
代理商： STM32F105RBT7XXX
Electrical characteristics
STM32F105xx, STM32F107xx
68/95
Doc ID 15274 Rev 4
CAN (controller area network) interface
Refer to Section 5.3.12: I/O port characteristics for more details on the input/output alternate
function characteristics (CANTX and CANRX).
5.3.16
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under the ambient temperature, fPCLK2 frequency and VDDA supply voltage
conditions summarized in Table 9.
Note:
It is recommended to perform a calibration after each power-up.
Table 50.
Dynamics characteristics: Ethernet MAC signals for MII(1)
1. TBD stands for to be determined.
Symbol
Rating
Min
Typ
Max
Unit
tsu(RXD)
Receive data setup time
TBD
ns
tih(RXD)
Receive data hold time
TBD
ns
tsu(DV)
Data valid setup time
TBD
ns
tih(DV)
Data valid hold time
TBD
ns
tsu(ER)
Error setup time
TBD
ns
tih(ER)
Error hold time
TBD
ns
td(TXEN)
Transmit enable valid delay time
13.4
15.5
17.7
ns
td(TXD)
Transmit data valid delay time
12.9
16.1
19.4
ns
Table 51.
ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Power supply
2.4
3.6
V
VREF+ Positive reference voltage
2.4
VDDA
V
IVREF
Current on the VREF input pin
160(1)
220(1)
A
fADC
ADC clock frequency
0.6
14
MHz
fS
(2)
Sampling rate
0.05
1
MHz
fTRIG
(2)
External trigger frequency
fADC = 14 MHz
823
kHz
17
1/fADC
VAIN
Conversion voltage range(3)
0 (VSSA or VREF-
tied to ground)
VREF+
V
RAIN
(2)
External input impedance
See Equation 1 and
Table 52 for details
50
k
RADC
(2)
Sampling switch resistance
1
k
CADC
(2)
Internal sample and hold capacitor
8
pF
tCAL
(2)
Calibration time
fADC = 14 MHz
5.9
s
83
1/fADC
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相关代理商/技术参数
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