参数资料
型号: STM32F105VBH7XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
封装: ROHS COMPLIANT, LFBGA-100
文件页数: 10/90页
文件大小: 998K
代理商: STM32F105VBH7XXX
Description
STM32F105xx, STM32F107xx
(twisted-pair, fiber, etc.). the PHY is connected to the STM32F107xx MII port using as many
as 17 signals (MII) or 9 signals (RMII) and can be clocked using the 25 MHz (MII) or 50 MHz
(RMII) output from the STM32F107xx.
The STM32F107xx includes the following features:
Supports 10 and 100 Mbit/s rates
Dedicated DMA channel
Tagged MAC frame support (VLAN support)
Half-duplex (CSMA/CD) and full-duplex operation
MAC control sublayer (control frames) support
32-bit CRC generation and removal
Several address filtering modes for physical and multicast address (multicast and group
addresses)
32-bit status code for each transmitted or received frame
Internal FIFOs to buffer transmit and receive frames. The transmit FIFO and the receive
FIFO are both 2 Kbytes (512 × 35 bits), that is 4 Kbytes in total
Supports hardware PTP (precision time protocol) in accordance with IEEE 1588 1.0
with the timestamp comparator connected to the TIM2 trigger input
Triggers interrupt when system time becomes greater than target time
2.4.12
Controller area network (CAN)
The two CANs are compliant with the 2.0A and B (active) specifications with a bitrate up to
1 Mbit/s. They can receive and transmit standard frames with 11-bit identifiers as well as
extended frames with 29-bit identifiers. Each CAN has three transmit mailboxes, two receive
FIFOS with 3 stages and 28 shared scalable filter banks (all of them can be used even if one
CAN is used). The 256 bytes of SRAM which are allocated for each CAN (512 bytes in total)
are not shared with any other peripheral.
2.4.13
Universal serial bus on-the-go full-speed (USB OTG FS)
The STM32F105xx and STM32F107xx connectivity line devices embed a USB OTG full-
speed (12 Mb/s) device/host/OTG peripheral with integrated transceivers. The USB OTG FS
peripheral is compliant with the USB 2.0 specification and with the OTG 1.0 specification. It
has software-configurable endpoint setting and supports suspend/resume. The USB OTG
full-speed controller requires a dedicated 48 MHz clock that is generated by a PLL
connected to the HSE oscillator. The major features are:
1.25 KB of SRAM used exclusively by the endpoints (not shared with any other
peripheral)
4 bidirectional endpoints
HNP/SNP/IP inside (no need for any external resistor)
for OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
the SOF output can be used to synchronize the external audio DAC clock in
isochronous mode
in accordance with the USB 2.0 Specification, the supported transfer speeds are:
in Host mode: full speed and low speed
in Device mode: full speed
相关PDF资料
PDF描述
STM32F105VCH6TR 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
STM32F105VCH7XXX 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
STM32F107VBH6TR 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
STM32F107VBH7TR 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
STM32F107VBT7XXX 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PQFP100
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