参数资料
型号: STM32F105VBH7XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
封装: ROHS COMPLIANT, LFBGA-100
文件页数: 5/90页
文件大小: 998K
代理商: STM32F105VBH7XXX
STM32F105xx, STM32F107xx
Description
interrupt management of the PLL clock entry is available when necessary (for example with
failure of an indirectly used external oscillator).
A single 25 MHz crystal can clock the entire system including the ethernet and USB OTG
FS peripherals. Several prescalers and PLLs allow the configuration of the AHB frequency,
the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum
frequency of the AHB and the high speed APB domains is 72 MHz. The maximum allowed
frequency of the low speed APB domain is 36 MHz. Refer to Figure 50: USB OTG FS +
The advanced clock controller clocks the core and all peripherals using a single crystal or
oscillator. In order to achieve audio class performance, an audio crystal can be used. In this
case, the I2S master clock can generate all standard sampling frequencies from 8 kHz to
96 kHz with less than 0.5% accuracy error. Refer to Figure 51: USB OTG FS + I2S (Audio)
To configure the PLLs, please refer to Table 60 on page 88, which provides PLL
configurations according to the application type.
2.3.8
Boot modes
At startup, boot pins are used to select one of three boot options:
Boot from User Flash
Boot from System Memory
Boot from embedded SRAM
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1, USART2 (remapped), CAN2 (remapped), USB OTG FS in device mode
(DFU: device firmware upgrade) and Ethernet.
2.3.9
Power supply schemes
VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator.
Provided externally through VDD pins.
VSSA, VDDA = 2.0 to 3.6 V: external analog power supplies for ADC, Reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 2.4 V when the ADC is used). VDDA
and VSSA must be connected to VDD and VSS, respectively.
VBAT = 1.8 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup
registers (through power switch) when VDD is not present.
2.3.10
Power supply supervisor
The device has an integrated power-on reset (POR)/power-down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when VDD is below a specified threshold, VPOR/PDR, without the need for an
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher
than the VPVD threshold. The interrupt service routine can then generate a warning
message and/or put the MCU into a safe state. The PVD is enabled by software.
相关PDF资料
PDF描述
STM32F105VCH6TR 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
STM32F105VCH7XXX 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
STM32F107VBH6TR 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
STM32F107VBH7TR 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, BGA100
STM32F107VBT7XXX 32-BIT, FLASH, 72 MHz, RISC MICROCONTROLLER, PQFP100
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