参数资料
型号: STM32F205REY6XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 120 MHz, RISC MICROCONTROLLER, PBGA66
封装: 0.40 MM PITCH, ROHS COMPLIANT, WLCSP-66
文件页数: 144/163页
文件大小: 2275K
代理商: STM32F205REY6XXX
STM32F205xx, STM32F207xx
Electrical characteristics
Doc ID 15818 Rev 7
tLOCK
PLL lock time
VCO freq = 192 MHz
75
-
200
s
VCO freq = 432 MHz
100
-
300
Jitter(3)
Cycle-to-cycle jitter
System clock
120 MHz
RMS
-
25
-
ps
peak
to
peak
-
±150
-
Period Jitter
RMS
-
15
-
peak
to
peak
-
±200
-
Main clock output (MCO) for
RMII Ethernet
Cycle to cycle at 50 MHz
on 1000 samples
-32
-
Main clock output (MCO) for MII
Ethernet
Cycle to cycle at 25 MHz
on 1000 samples
-40
-
Bit Time CAN jitter
Cycle to cycle at 1 MHz
on 1000 samples
-330
-
IDD(PLL)
(4)
PLL power consumption on VDD
VCO freq = 192 MHz
VCO freq = 432 MHz
0.15
0.45
-
0.40
0.75
mA
IDDA(PLL)
PLL power consumption on
VDDA
VCO freq = 192 MHz
VCO freq = 432 MHz
0.30
0.55
-
0.40
0.85
mA
1.
Take care of using the appropriate division factor M to obtain the specified PLL input clock values. The M factor is shared
between PLL and PLLI2S.
2.
Guaranteed by design, not tested in production.
3.
The use of 2 PLLs in parallel could degraded the Jitter up to +30%.
4.
Based on characterization, not tested in production.
Table 29.
Main PLL characteristics (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 30.
PLLI2S (audio PLL) characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fPLLI2S_IN
PLLI2S input clock(2)
0.95(3)
12.1(3)
MHz
fPLLI2S_OUT
PLLI2S multiplier output clock
-
216
MHz
fVCO_OUT
PLLI2S VCO output
192
-
432
MHz
tLOCK
PLLI2S lock time
VCO freq = 192 MHz
75
-
200
s
VCO freq = 432 MHz
100
-
300
相关PDF资料
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