参数资料
型号: STM32F205REY6XXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 32-BIT, FLASH, 120 MHz, RISC MICROCONTROLLER, PBGA66
封装: 0.40 MM PITCH, ROHS COMPLIANT, WLCSP-66
文件页数: 89/163页
文件大小: 2275K
代理商: STM32F205REY6XXX
STM32F205xx, STM32F207xx
Description
Doc ID 15818 Rev 7
suspend/resume. The USB OTG full-speed controller requires a dedicated 48 MHz clock
that is generated by a PLL connected to the HSE oscillator. The major features are:
Combined Rx and Tx FIFO size of 1024× 35 bits with dynamic FIFO sizing
Supports the session request protocol (SRP) and host negotiation protocol (HNP)
6 bidirectional endpoints
12 host channels with periodic OUT support
Internal FS OTG PHY support
External FS OTG PHY support through an I2C connection
External HS or HS OTG operation supporting ULPI in SDR mode. The OTG PHY is
connected to the microcontroller ULPI port through 12 signals. It can be clocked using
the 60 MHz output.
Internal USB DMA
HNP/SNP/IP inside (no need for any external resistor)
For OTG/Host modes, a power switch is needed in case bus-powered devices are
connected
2.2.35
Audio PLL (PLLI2S)
The devices feature an additional dedicated PLL for audio I2S application. It allows to
achieve error-free I2S sampling clock accuracy without compromising on the CPU
performance, while using USB peripherals.
The PLLI2S configuration can be modified to manage an I2S sample rate change without
disabling the main PLL (PLL) used for CPU, USB and Ethernet interfaces.
The audio PLL can be programmed with very low error to obtain sampling rates ranging
from 8 kHz to 192 kHz.
In addition to the audio PLL, a master clock input pin can be used to synchronize the I2S
flow with an external PLL (or Codec output).
2.2.36
Digital camera interface (DCMI)
The camera interface is not available in STM32F205xx devices.
STM32F207xx products embed a camera interface that can connect with camera modules
and CMOS sensors through an 8-bit to 14-bit parallel interface, to receive video data. The
camera interface can sustain up to 27 Mbyte/s at 27 MHz or 48 Mbyte/s at 48 MHz. It
features:
Programmable polarity for the input pixel clock and synchronization signals
Parallel data communication can be 8-, 10-, 12- or 14-bit
Supports 8-bit progressive video monochrome or raw Bayer format, YCbCr 4:2:2
progressive video, RGB 565 progressive video or compressed data (like JPEG)
Supports continuous mode or snapshot (a single frame) mode
Capability to automatically crop the image
2.2.37
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain,
with or without pull-up or pull-down), as input (floating, with or without pull-up or pull-down)
or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog
相关PDF资料
PDF描述
STM32F205RFT6TR 32-BIT, FLASH, 120 MHz, RISC MICROCONTROLLER, PQFP64
STM32F205RFT7XXX 32-BIT, FLASH, 120 MHz, RISC MICROCONTROLLER, PQFP64
STM32F205RFY6TR 32-BIT, FLASH, 120 MHz, RISC MICROCONTROLLER, PBGA66
STM32F205RGT7TR 32-BIT, FLASH, 120 MHz, RISC MICROCONTROLLER, PQFP64
STM32F205RGY7TR 32-BIT, FLASH, 120 MHz, RISC MICROCONTROLLER, PBGA66
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