STM690/704/795/802/804/805/806
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Pin Descriptions
MR.
A logic low on /MR asserts the reset output.
Reset remains asserted as long as MR is low and
for t
rec
after MR returns high. This active-low input
has an internal pull-up. It can be driven from a TTL
or CMOS logic line, or shorted to ground with a
switch. Leave open if unused.
WDI.
If WDI remains high or low for 1.6sec, the in-
ternal watchdog timer runs out and reset is trig-
gered. The internal watchdog timer clears while
reset is asserted or when WDI sees a rising or fall-
ing edge.
The watchdog function cannot be disabled by al-
lowing the WDI pin to float.
RST.
Pulses low for t
rec
when triggered, and stays
low whenever V
CC
is below the reset threshold or
when MR is a logic low. It remains low for t
rec
after
either V
CC
rises above the reset threshold, the
watchdog triggers a reset, or MR goes from low to
high.
RST (Open Drain).
Pulses high for t
rec
when trig-
gered, and stays high whenever V
CC
is above the
reset threshold or when MR is a logic high. It re-
mains high for t
rec
after either V
CC
falls below the
reset threshold, the watchdog triggers a reset, or
MR goes from high to low.
PFI.
When PFI is less than V
PFI
or when V
CC
falls
below V
SW
(2.4V), PFO goes low; otherwise, PFO
remains high. Connect to ground if unused.
PFO.
When PFI is less than V
PFI
, or V
CC
falls be-
low V
SW
, PFO goes low; otherwise, PFO remains
high. Leave open if unused.
V
OUT
.
When V
CC
is above the switchover voltage
(V
SO
), V
OUT
is connected to V
CC
through a P-
channel MOSFET switch. When V
CC
falls below
V
SO
, V
BAT
connects to V
OUT
. Connect to V
CC
if no
battery is used.
Vccsw.
When V
OUT
switches to battery, Vccsw is
high. When V
OUT
switches back to V
CC
, Vccsw is
low. It can be used to drive gate of external PMOS
transistor for I
OUT
requirements exceeding 75mA.
E.
The input to the chip-enable gating circuit. Con-
nect to ground if unused.
E
CON
.
E
CON
goes low only when E is low and re-
set is not asserted. If E
CON
is low when reset is as-
serted, E
CON
will remain low for 15μs or until E
goes high, whichever occurs first. In the disabled
mode, E
CON
is pulled up to V
OUT
.
V
BAT
.
When V
CC
falls below V
SO
, V
OUT
switches
from V
CC
to V
BAT
. When V
CC
rises above V
SO
+
hysteresis, V
OUT
reconnects to V
CC
. V
BAT
may ex-
ceed V
CC
. Connect to V
CC
if no battery is used.
Table 3. Pin Description
Pin
Name
Function
STM795
STM690
STM802
STM704
STM806
STM804
STM805
–
–
6
–
MR
Push-button Reset Input
–
6
–
6
WDI
Watchdog Input
7
7
7
–
RST
Active-Low Reset Output
–
–
–
7
RST
Active-High Reset Output
–
4
4
4
PFI
PFI Power-fail Input
–
5
5
5
PFO
PFO Power-fail Output
1
1
1
1
V
OUT
Supply Output for External LPSRAM
2
2
2
2
V
CC
Supply Voltage
3
–
–
–
Vccsw
V
CC
Switch Output
4
3
3
3
V
SS
Ground
5
–
–
–
E
Chip Enable Input
6
–
–
–
E
CON
Conditioned Chip Enable Output
8
8
8
8
V
BAT
Backup-Battery Input