参数资料
型号: STM8AF51AATBXXXX
厂商: STMICROELECTRONICS
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP80
封装: 14 X 14 MM, ROHS COMPLIANT, LQFP-80
文件页数: 7/118页
文件大小: 2173K
代理商: STM8AF51AATBXXXX
Known limitations
STM8AF51xx, STM8AF61xx
104/118
Doc ID 14395 Rev 6
Workaround
Reset the AL bit at least two instructions before the IRET instruction.
13.2
I2C interface
13.2.1
Misplaced NACK bit when receiving 2 bytes in master mode
Description
When receiving two bytes in master mode, the usual sequence is the following:
1.
Set POS and ACK bits of the I2C_CR2 register to 1.
2.
Wait for ADDR event (address sent bit in I2C_SR1 register). When ADDR is set to 1,
program ACK to 0 and clear ADDR.
3.
Wait for BTF event (byte transfer finished bit in I2C_SR1 register). When BTF is set to
1, program the STOP bit to 1 in the I2C_CR2 register, and read the 2 received bytes.
The NACK bit may be sent erroneously after the first byte.
Workaround
Use a different software sequence to clear ADDR and ACK bits:
1.
Wait till ADDR flag is set.
2.
Mask interrupts.
3.
Clear ADDR bit.
4.
Clear ACK bit.
5.
Re-enable interrupts.
As the TLI interrupt is not maskable, this software workaround can not be implemented in
applications using the TLI interrupt.
13.2.2
Data register corrupted
Description
The content of the shift register may be shifted to the left by 1 bit and the second read
operation will return an incorrect value when the following conditions are met:
BTF bit (last data received) set to 1
Software sequence (SET STOP, READ N-1, READ N) delayed (for instance by an
interrupt)
N-1 byte not read before the next SCL rising edge.
Workaround
Mask all active interrupts between the SET STOP and the READ N-1 instructions. As TLI is
not maskable, this software workaround can not be implemented in applications using the
TLI interrupt.
相关PDF资料
PDF描述
STM8AF6179TCXXXY 8-BIT, FLASH, 24 MHz, MICROCONTROLLER, PQFP64
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